On Mon, Jan 12, 2009 at 05:37:39PM +0100, Dimitry Andric wrote:
> On 2009-01-12 07:41, Pyun YongHyeon wrote:
> > I see, Unfortunately the issue was fixed in the end of 7.1-R
> > release process so I wanted to get more exposure before MFC.
> > I'll make sure to MFC to stable/7 after more testing.
>
> I'm also having problems with re's, in my case the interfaces take about
> 10 seconds to come up, if they come up at all. After the interfaces are
> up, half the time no packets go out at all. Usually it helps to bring
> them down via the console, wait about 10 seconds, and then bring them up
> again...
>
It looks like that RTL8169SC users see regression and I vaguely
remember a couple of issues on RTL8169SC. As Jung-uk said in other
post, would yoy try reverting r180519? If that have no effect would
you try attached patch?
> These are the following variant:
>
> FreeBSD 7.1-STABLE #0: Mon Jan 12 14:22:11 CET 2009
> [...]
> re0: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xf000-0xf0ff
> mem 0xfdfff000-0xfdfff0ff irq 18 at device 9.0 on pci0
> re0: Chip rev. 0x18000000
> re0: MAC rev. 0x00000000
> miibus0: <MII bus> on re0
> rgephy0: <RTL8169S/8110S/8211B media interface> PHY 1 on miibus0
> rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
> 1000baseT-FDX, auto
> re0: Ethernet address: 00:30:18:a6:f1:a8
> re0: [FILTER]
> re1: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xf200-0xf2ff
> mem 0xfdffe000-0xfdffe0ff irq 19 at device 11.0 on pci0
> re1: Chip rev. 0x18000000
> re1: MAC rev. 0x00000000
> miibus1: <MII bus> on re1
> rgephy1: <RTL8169S/8110S/8211B media interface> PHY 1 on miibus1
> rgephy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
> 1000baseT-FDX, auto
> re1: Ethernet address: 00:30:18:a6:f1:a9
> re1: [FILTER]
>
> And just FYI, r187080-r187083 that you recently committed (MFCs of
> r184240-184243, r184245, 185575 and r186390), don't seem to change
> anything for this situation. :(
Those MFC are for rl(4), not re(4) so you should see no behavioural
changes in re(4).
--
Regards,
Pyun YongHyeon
Index: sys/dev/re/if_re.c
===================================================================
--- sys/dev/re/if_re.c (revision 187123)
+++ sys/dev/re/if_re.c (working copy)
@@ -1295,6 +1295,8 @@
case RL_HWREV_8169_8110SC:
case RL_HWREV_8169_8110SBL:
sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHY8169;
+ if (hw_rev->rl_rev == RL_HWREV_8169_8110SC)
+ sc->rl_flags |= 0x10000;
break;
default:
break;
@@ -2504,6 +2506,7 @@
uint32_t align_dummy;
u_char eaddr[ETHER_ADDR_LEN];
} eaddr;
+ int clk66;
RL_LOCK_ASSERT(sc);
@@ -2534,6 +2537,29 @@
} else
cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
+ if ((sc->rl_flags & 0x10000) != 0) {
+ clk66 = (CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0;
+ switch (CSR_READ_4(sc, RL_TXCFG) & 0xFC800000) {
+ case 0x18000000:
+ /* 8169/8110SCd */
+ if (clk66 > 0)
+ CSR_WRITE_4(sc, 0x7C, 0x000FFFFF);
+ else
+ CSR_WRITE_4(sc, 0x7C, 0x009FFFFF);
+ break;
+ case 0x98000000:
+ /* 8169/8110SCe */
+ if (clk66 > 0)
+ CSR_WRITE_4(sc, 0x7C, 0x000FFF00);
+ else
+ CSR_WRITE_4(sc, 0x7C, 0x009FFF00);
+ break;
+ default:
+ break;
+ }
+ /* Disable interrupt mitigation. */
+ CSR_WRITE_2(sc, 0xE2, 0);
+ }
/*
* Disable TSO if interface MTU size is greater than MSS
* allowed in controller.
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