On Thu, May 09, 2013 at 11:42:28AM -0400, Jim Ohlstein wrote:
> On 05/09/13 10:30, Konstantin Belousov wrote:
> > On Thu, May 09, 2013 at 10:13:15AM -0400, Jim Ohlstein wrote:
> >> # sysctl hw.model
> >> hw.model: AMD FX(tm)-8350 Eight-Core Processor
> > Ahh, so it seems that this is a CPU with the LWP.
> > Please try the patch at the end of message.
> 
> Same error
> 
> >
> > As another workaround, which does not disable AVX support, you
> > could try loader tunable hw.xsave_mask=0x7.
> 
> This works

Hm, I see another bug in the next line as well.  Could you try this
updated patch ?

diff --git a/sys/amd64/amd64/fpu.c b/sys/amd64/amd64/fpu.c
index de79baa..9bc8a2f 100644
--- a/sys/amd64/amd64/fpu.c
+++ b/sys/amd64/amd64/fpu.c
@@ -687,8 +687,8 @@ fpugetregs(struct thread *td)
                    offsetof(struct xstate_hdr, xstate_bv));
                max_ext_n = flsl(xsave_mask);
                for (i = 0; i < max_ext_n; i++) {
-                       bit = 1 << i;
-                       if ((*xstate_bv & bit) != 0)
+                       bit = 1ULL << i;
+                       if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
                                continue;
                        bcopy((char *)fpu_initialstate +
                            xsave_area_desc[i].offset,

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