On Wednesday, 30 March 2005 at 23:01:03 -0500, John Baldwin wrote:
On Mar 30, 2005, at 8:54 PM, Greg 'groggy' Lehey wrote:
lapic0: LINT1 trigger: edge lapic0: LINT1 polarity: high lapic1: Routing NMI -> LINT1 lapic1: LINT1 trigger: edge lapic1: LINT1 polarity: high -ioapic0 <Version 0.3> irqs 0-23 on motherboard +ioapic0 <Version 0.0> irqs 0-23 on motherboard cpu0 BSP: ID: 0x00000000 VER: 0x00040010 LDR: 0x01000000 DFR: 0x0fffffff lint0: 0x00010700 lint1: 0x00000400 TPR: 0x00000000 SVR: 0x000001ff
This shows that in the - case the APIC is broken somehow (0.0 isn't a
valid I/O APIC version).
You mean the + case, I suppose. Yes, that's what I suspected.
It would seem that the system has mapped RAM over top of the I/O APIC perhaps?
That's what I suspected too, but imp doesn't think so.
I'd be more inclined to believe that there is an erroneous mapping by the OS, not that things are fundamentally broken in hardware. Your SMAP table shows everything correctly. It's becoming hard to break through
your pre-concieved notions here and explain how things actually work.
It would be interesting to see the contents of your MADT to see if it's trying to use a 64-bit PA for your APIC.
Any suggestions about how to do so?
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