Салям!
31-Янв-2004 18:15 [EMAIL PROTECTED] (Patrick J. LoPresti) wrote to
[EMAIL PROTECTED]:
PJL> Issue 2 (interrupts) is a potential problem for the original approach,
PJL> because cmpsd is interruptible. So if A20 is disabled and the bytes
PJL> in low memory change during an interrupt, the comparison might fail
PJL> and give the wrong answer.
My (Pentium) manual says, that interrupt is consistent in comparision,
i.e. rep cmps is suspended between, not inside comparision. So, I not see
how you may cause fail in comparision memory area with itself.
PJL> With the new code, there is a potential problem if an interrupt negates
PJL> FFFFh:10h when the A20 gate is open. One could argue that none of this
PJL> is very likely.
Yes, this is probable, but very unlikely. On the other side, this is
impossible to prevent multi-instruction transaction (write ds:0, read ds:0,
read es:10; or, at least, write ds:0, read es:10) with interrupts enabled.
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