On Thu, May 10, 2018 at 01:59:38PM +0530, Rajesh Yadav wrote:
> Current MSM display controller HW matches a tree like
> hierarchy where MDSS top level wrapper is parent device
> and mdp5/dpu, dsi, dp are child devices.
>
> Each child device like mdp5, dsi etc. have a separate driver,
> but currently dpu handling is tied to a single driver which
> was managing both mdss and dpu resources.
>
> Inorder to have the cleaner one to one device and driver
> association, this change adds a new platform_driver for dpu
> child device node which implements the kms functionality.
>
> The dpu driver implements runtime_pm support for managing clocks
> and bus bandwidth etc.
>
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 251
> ++++++++++++++++++++++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 +
> drivers/gpu/drm/msm/msm_drv.c | 2 +
> drivers/gpu/drm/msm/msm_drv.h | 3 +
> 4 files changed, 214 insertions(+), 46 deletions(-)
<snip>
> if (!kms) {
> @@ -1565,34 +1548,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
> goto end;
> }
>
> - platformdev = to_platform_device(dev->dev);
> - if (!platformdev) {
> - DPU_ERROR("invalid platform device\n");
> - goto end;
> - }
> -
> priv = dev->dev_private;
> if (!priv) {
> DPU_ERROR("invalid private data\n");
> goto end;
> }
>
> - dpu_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
> + dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys");
> if (IS_ERR(dpu_kms->mmio)) {
> rc = PTR_ERR(dpu_kms->mmio);
> DPU_ERROR("mdp register memory map failed: %d\n", rc);
> dpu_kms->mmio = NULL;
> goto error;
> }
> - DRM_INFO("mapped mdp address space @%p\n", dpu_kms->mmio);
> - dpu_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
> + DRM_INFO("mapped dpu address space @%p\n", dpu_kms->mmio);
This is not a useful message - move to debug or remove. In any event, please
don't use %p.
> + dpu_kms->mmio_len = msm_iomap_size(dpu_kms->pdev, "mdp_phys");
> rc = dpu_dbg_reg_register_base(DPU_DBG_NAME, dpu_kms->mmio,
> dpu_kms->mmio_len);
> if (rc)
> DPU_ERROR("dbg base register kms failed: %d\n", rc);
>
> - dpu_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
> + dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif_phys",
> "vbif_phys");
> if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
> rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
> @@ -1600,20 +1577,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
> dpu_kms->vbif[VBIF_RT] = NULL;
> goto error;
> }
> - dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
> + dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(dpu_kms->pdev,
> "vbif_phys");
> rc = dpu_dbg_reg_register_base("vbif_rt", dpu_kms->vbif[VBIF_RT],
> dpu_kms->vbif_len[VBIF_RT]);
> if (rc)
> DPU_ERROR("dbg base register vbif_rt failed: %d\n", rc);
>
> - dpu_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
> + dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt_phys",
>
> "vbif_nrt_phys");
> if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
> dpu_kms->vbif[VBIF_NRT] = NULL;
> DPU_DEBUG("VBIF NRT is not defined");
> } else {
> - dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
> + dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(dpu_kms->pdev,
> "vbif_nrt_phys");
> rc = dpu_dbg_reg_register_base("vbif_nrt",
> dpu_kms->vbif[VBIF_NRT],
> @@ -1624,13 +1601,13 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
> }
>
> #ifdef CONFIG_CHROME_REGDMA
> - dpu_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
> + dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma_phys",
> "regdma_phys");
> if (IS_ERR(dpu_kms->reg_dma)) {
> dpu_kms->reg_dma = NULL;
> DPU_DEBUG("REG_DMA is not defined");
> } else {
> - dpu_kms->reg_dma_len = msm_iomap_size(platformdev,
> + dpu_kms->reg_dma_len = msm_iomap_size(dpu_kms->pdev,
> "regdma_phys");
> rc = dpu_dbg_reg_register_base("reg_dma",
> dpu_kms->reg_dma,
> @@ -1804,14 +1781,13 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
> dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
> pm_runtime_put_sync(dev->dev);
> error:
> - _dpu_kms_hw_destroy(dpu_kms, platformdev);
> + _dpu_kms_hw_destroy(dpu_kms);
> end:
> return rc;
> }
>
> struct msm_kms *dpu_kms_init(struct drm_device *dev)
> {
> - struct platform_device *pdev = to_platform_device(dev->dev);
> struct msm_drm_private *priv;
> struct dpu_kms *dpu_kms;
> int irq;
> @@ -1821,24 +1797,207 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
> return ERR_PTR(-EINVAL);
> }
>
> - irq = platform_get_irq(pdev, 0);
> + priv = dev->dev_private;
> + dpu_kms = to_dpu_kms(priv->kms);
> +
> + irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
> if (irq < 0) {
> DPU_ERROR("failed to get irq: %d\n", irq);
> return ERR_PTR(irq);
> }
> + dpu_kms->base.irq = irq;
>
> - priv = dev->dev_private;
> + return &dpu_kms->base;
> +}
> +
> +static void dpu_destroy(struct platform_device *pdev)
> +{
> + struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> + struct dss_module_power *mp = &dpu_kms->mp;
> +
> + msm_dss_put_clk(mp->clk_config, mp->num_clk);
> + devm_kfree(&pdev->dev, mp->clk_config);
> + mp->num_clk = 0;
> +
> + if (dpu_kms->rpm_enabled)
> + pm_runtime_disable(&pdev->dev);
> +
> + devm_kfree(&pdev->dev, dpu_kms);
> +}
>
> - dpu_kms = kzalloc(sizeof(*dpu_kms), GFP_KERNEL);
> +static int dpu_init(struct platform_device *pdev, struct drm_device *dev)
> +{
> + struct msm_drm_private *priv = dev->dev_private;
> + struct dpu_kms *dpu_kms;
> + struct dss_module_power *mp;
> + int ret = 0;
> +
> + dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
> if (!dpu_kms) {
> DPU_ERROR("failed to allocate dpu kms\n");
As long as you are nearby, remove this log message.
> - return ERR_PTR(-ENOMEM);
> + return -ENOMEM;
> + }
> +
> + mp = &dpu_kms->mp;
> + ret = msm_dss_parse_clock(pdev, mp);
> + if (ret) {
> + DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
> + goto clk_parse_error;
> + }
> +
> + ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
> + if (ret) {
> + pr_err("failed to get clocks, ret=%d\n", ret);
> + goto clk_get_error;
> + }
> +
> + ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
> + if (ret) {
> + pr_err("failed to set clock rate, ret=%d\n", ret);
> + goto clk_rate_error;
> }
>
> + platform_set_drvdata(pdev, dpu_kms);
> +
> msm_kms_init(&dpu_kms->base, &kms_funcs);
> dpu_kms->dev = dev;
> - dpu_kms->base.irq = irq;
> + dpu_kms->pdev = pdev;
>
> - return &dpu_kms->base;
> + pm_runtime_enable(&pdev->dev);
> + dpu_kms->rpm_enabled = true;
> +
> + priv->kms = &dpu_kms->base;
> +
> + return ret;
> +
> +clk_rate_error:
> + msm_dss_put_clk(mp->clk_config, mp->num_clk);
> +clk_get_error:
> + devm_kfree(&pdev->dev, mp->clk_config);
> + mp->num_clk = 0;
> +clk_parse_error:
> + devm_kfree(&pdev->dev, dpu_kms);
> +
> + return ret;
> +}
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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