This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now
supported by the freedreno driver.

The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm
driver to identify the smaller 128KiB GMEM size.

Signed-off-by: Jonathan Marek <jonat...@marek.ca>
---
v4:
 added commit message
 moved to follow address order
 removed frequencies, they are not needed as clocks have fixed rate

 arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++
 arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 67d462715..14dcc5a41 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -123,6 +123,16 @@
                        reg = <0x1ffe0000 0x20000>;
                };
 
+               gpu: gpu@30000000 {
+                       compatible = "amd,imageon-200.1", "amd,imageon";
+                       reg = <0x30000000 0x20000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+                       interrupts = <12>;
+                       interrupt-names = "kgsl_3d0_irq";
+                       clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks 
IMX5_CLK_GARB_GATE>;
+                       clock-names = "core_clk", "mem_iface_clk";
+               };
+
                ipu: ipu@40000000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 207eb557c..d7d5fe4c7 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -209,6 +209,16 @@
                        };
                };
 
+               gpu: gpu@30000000 {
+                       compatible = "amd,imageon-200.0", "amd,imageon";
+                       reg = <0x30000000 0x20000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+                       interrupts = <12>;
+                       interrupt-names = "kgsl_3d0_irq";
+                       clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks 
IMX5_CLK_GARB_GATE>;
+                       clock-names = "core_clk", "mem_iface_clk";
+               };
+
                aips@50000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
-- 
2.17.1

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