On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote: > On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote: > > On 28.05.2023 19:07, Manivannan Sadhasivam wrote: > > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote: > > >> On 23.05.2023 03:15, Bjorn Andersson wrote: > > >>> From: Bjorn Andersson <bjorn.anders...@linaro.org> [..] > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > >>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi [..] > > >>> + gmu: gmu@3d6a000 { [..] > > >>> + status = "disabled"; > > >> I've recently discovered that - and I am not 100% sure - all GMUs are > > >> cache-coherent. Could you please ask somebody at qc about this? > > >> > > > > > > AFAIU, GMU's job is controlling the voltage and clock to the GPU. > > Not just that, it's only the limited functionality we've implemented > > upstream so far. > > > > Okay, good to know! > > > It doesn't do > > > any data transactions on its own. > > Of course it does. AP communication is done through MMIO writes and > > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some > > of the GPU registers (that nota bene don't have anything to do with > > the GMU M3 core itself) lay within the GMU address space. > >
But those aren't shared memory accesses. > > That doesn't justify the fact that cache coherency is needed, especially > MMIO writes, unless GMU could snoop the MMIO writes to AP caches. > In reviewing the downstream state again I noticed that the GPU smmu is marked dma-coherent, so I will adjust that in v3. Regards, Bjorn