[PATCH v2 17/19] drm/msm/dpu: modify timing engine programming for YUV420 over DP

[Paloma Arellano]

Adjust the encoder timing engine setup programming in the case of video
mode for YUV420 over DP to accommodate CDM.

Changes in v2:
        - Move timing engine programming to this patch

Signed-off-by: Paloma Arellano <quic_parel...@quicinc.com>
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 3f102b2813ca8..fb46d907312a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -235,8 +235,9 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
 {
        struct drm_display_mode mode;
        struct dpu_hw_intf_timing_params timing_params = { 0 };
+       struct dpu_hw_cdm *hw_cdm;
        const struct dpu_format *fmt = NULL;
-       u32 fmt_fourcc = DRM_FORMAT_RGB888;
+       u32 fmt_fourcc;
        unsigned long lock_flags;
        struct dpu_hw_intf_cfg intf_cfg = { 0 };
 
@@ -255,17 +256,21 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
        DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
        drm_mode_debug_printmodeline(&mode);
 
-       if (phys_enc->split_role != ENC_ROLE_SOLO) {
+       fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
+
+       if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == 
DRM_FORMAT_YUV420) {
                mode.hdisplay >>= 1;
                mode.htotal >>= 1;
                mode.hsync_start >>= 1;
                mode.hsync_end >>= 1;
+               mode.hskew >>= 1;
 
                DPU_DEBUG_VIDENC(phys_enc,
-                       "split_role %d, halve horizontal %d %d %d %d\n",
+                       "split_role %d, halve horizontal %d %d %d %d %d\n",
                        phys_enc->split_role,
                        mode.hdisplay, mode.htotal,
-                       mode.hsync_start, mode.hsync_end);
+                       mode.hsync_start, mode.hsync_end,
+                       mode.hskew);
        }
 
        drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
@@ -273,6 +278,9 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
        fmt = dpu_get_dpu_format(fmt_fourcc);
        DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
 
+       hw_cdm = phys_enc->hw_cdm;
+       if (hw_cdm)
+               intf_cfg.cdm = hw_cdm->idx;
        intf_cfg.intf = phys_enc->hw_intf->idx;
        intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
        intf_cfg.stream_sel = 0; /* Don't care value for video mode */
-- 
2.39.2