On Thu, Apr 04, 2024 at 04:43:44PM -0700, Stephen Boyd wrote: > Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to > setup clocks") changed the offset that is used to write to > DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to > QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different > between v3 and v4 phys: > > #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 > #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 > > meaning that we write the wrong register on v3 phys now. Add another > generic register to 'regs' and use it here instead of a version specific > define to fix this. > > This was discovered after Abhinav looked over register dumps with me > from sc7180 Trogdor devices that started failing to light up the > external display with v6.6 based kernels. It turns out that some > monitors are very specific about their link clk frequency and if the > default power on reset value is still there the monitor will show a > blank screen or a garbled display. Other monitors are perfectly happy to > get a bad clock signal.
> Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup > clocks") > Signed-off-by: Stephen Boyd <swb...@chromium.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > index 7d585a4bbbba..3b19d8ebf467 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > @@ -77,6 +77,7 @@ enum qphy_reg_layout { > QPHY_COM_BIAS_EN_CLKBUFLR_EN, > > QPHY_DP_PHY_STATUS, > + QPHY_DP_PHY_VCO_DIV, > > QPHY_TX_TX_POL_INV, > QPHY_TX_TX_DRV_LVL, > @@ -102,6 +103,7 @@ static const unsigned int > qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { > + [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, > @@ -126,6 +128,7 @@ static const unsigned int > qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { > + [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, I happened to skim this patch on the list and noticed that you added a new register abstraction but only updated two tables. A quick look at the driver reveals that there are currently four such tables, which means that the v5_5nm (e.g. the Lenovo ThinkPad X13s) and v6 hardware would now be broken instead as they would write to offset 0. Clearly the hardware abstraction in this driver leaves a lot to wish for when it's this fragile, but how can three people including the maintainer review this change without this being noticed? I just sent a follow-up fix here: https://lore.kernel.org/lkml/20240408093023.506-1-johan+lin...@kernel.org/ > @@ -2184,7 +2188,7 @@ static int qmp_combo_configure_dp_clocks(struct > qmp_combo *qmp) > /* Other link rates aren't supported */ > return -EINVAL; > } > - writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); > + writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); Johan