On 9/22/2025 4:50 PM, Dmitry Baryshkov wrote:
On Mon, Sep 22, 2025 at 04:32:39PM -0700, Jessica Zhang wrote:
Since 3D merge allows for higher mode clocks to be supported across
multiple layer mixers, filter modes based on adjusted mode clocks
only if 3D merge isn't supported.
Reported-by: Abel Vesa <[email protected]>
Fixes: 62b7d6835288 ("drm/msm/dpu: Filter modes based on adjusted mode clock")
Signed-off-by: Jessica Zhang <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4b970a59deaf..5ac51863a189 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1549,7 +1549,8 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct
drm_crtc *crtc,
* The given mode, adjusted for the perf clock factor, should not exceed
* the max core clock rate
*/
- if (dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000)
+ if (!dpu_kms->catalog->caps->has_3d_merge &&
Well, not quite. If 3D merge is available, we should allow 2x of the
clock, instead of skipping the check completely. I don't think that we
should allow 8k or 16k just because the platform has 3D Mux.
Hi Dmitry,
Ack, I'll fix the math here.
Thanks,
Jessica Zhang
+ dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000)
return MODE_CLOCK_HIGH;
/*
---
base-commit: b5bad77e1e3c7249e4c0c88f98477e1ee7669b63
change-id: 20250922-modeclk-fix-a870375d9960
Best regards,
--
Jessica Zhang <[email protected]>
