On Sat, Feb 28, 2026 at 9:32 PM Dmitry Baryshkov <[email protected]> wrote: > > On Sat, Feb 28, 2026 at 06:19:07PM +0800, Pengyu Luo wrote: > > The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, > > utilizing the same register layouts and clock structures. > > > > However, DSI won't work properly for now until we submit dispcc fixes. > > And some DSC enabled panels require DPU timing calculation fixes too. > > (hdisplay / width timing round errors cause the fifo error) > > - Please squash refgen patch into this one.
Ack > - Please post at least the dispcc fixes. > Yes, it will come later with the panel driver. Lewis provided the patch but it was generated by Claude AI. The patch itself is not complicated, it only removes CLK_SET_RATE_PARENT from byte_div_clk_src dividers. But I need to find some time to analyze the dsi phy clock diagram and reword the commit log. Best wishes, Pengyu
