Hi Bruce, I may have asked this question before, but some part of the issue still doesn't make sense and hence the need for some clarification.
According to recon-all stages 4a and b should take 7.5hrs per hemisphere on a P3 1GHz machine. We have a P4 Xeon dual 2.8 GHz with enough memory and it takes somewhere between 6 and 7 hrs. Since the topology has already been fixed, shouldn't the timing of these stages scale inversely with processor speed? Are there other factors which influence the timing of these stages? Or a different way to put it, what should we do to get a speedup factor that a faster machine provides? A possibly related question, does freesurfer use operations on NaNs for any stage of computation? Thanks, Satra
