*To:* [email protected], [email protected] *From:* Taylor Christian Newsome
*Date:* August 20, 2025 *Dear Mellanox/NVIDIA Networking Support Team,* I am writing to formally submit the critical firmware parameters for Mellanox PCI Express Host Channel Adapter (HCA) cards, as detailed in the official documentation available here: https://content.mellanox.com/firmware/critical_params.txt. This document specifies essential configuration parameters that ensure optimal performance, power efficiency, and regulatory compliance for the following card families: - *Lion Cub / Lion Mini (P/N: MHEA28..., MHGA28...)* - *Tiger / Cheetah (P/N: MHES14..., MHES18..., MHGS18...)* Key details include SerDes static and dynamic settings, which are critical for maintaining hardware integrity and consistent operation. Alteration of these parameters could impact card performance and reliability. *Example Parameters for Lion Cub / Lion Mini Family:* - *SerDes Static Settings:* - port1_sd0_OBPreAmp = 0xf - port1_sd1_OBPreAmp = 0xf - port1_sd2_OBPreAmp = 0xf - port1_sd3_OBPreAmp = 0xf - port2_sd0_OBPreAmp = 0xf - port2_sd1_OBPreAmp = 0xf - port2_sd2_OBPreAmp = 0xf - port2_sd3_OBPreAmp = 0xf - *SerDes Dynamic Settings:* - auto_ddr_tx_options = 1 - auto_ddr_rx_options = 1 - auto_ddr_option_0.tx_preamp = 0xf - auto_ddr_option_1.tx_preamp = 0xf - ... (full details in the linked document) The Tiger / Cheetah family parameters follow a similar structure and should be preserved to maintain optimal operation. I recommend reviewing these parameters and ensuring they are maintained as specified. Please let me know if any further information or clarification is required. Thank you for your attention to this matter. *Sincerely,* Taylor Christian Newsome
Mellanox Technologies ********************* This file provides the lists of critical firmware parameters for PCI Express HCA cards by Mellanox Technologies. The card's performance, power consumption, and regulatory certification status are guaranteed by Mellanox Technologies as long as this set of critical parameters remains unchanged. The following tables are provided: Table 1: Critical Configuration Parameters for the Lion Cub / Lion Mini family (P/N: MHEA28..., MHGA28...) PCI-Ex Cards Table 2: Critical Configuration Parameters for the Tiger/Cheetah family (P/N: MHES14..., MHES18..., MHGS18...) PCI-Ex Cards *************************************************************************************************************************** Table 1: Critical Configuration Parameters for the Lion Cub / Lion Mini family (P/N: MHEA28..., MHGA28...) PCI-Ex Cards *************************************************************************************************************************** ;;;;; SerDes static parameters for OnlyDDR ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 0x0 - 0xf. port1_sd0_OBPreAmp = 0xf port1_sd1_OBPreAmp = 0xf port1_sd2_OBPreAmp = 0xf port1_sd3_OBPreAmp = 0xf port2_sd0_OBPreAmp = 0xf port2_sd1_OBPreAmp = 0xf port2_sd2_OBPreAmp = 0xf port2_sd3_OBPreAmp = 0xf ;;;;; Integer parameter. Values range : 0x1 - 0xf. port1_sd0_OBVoltage = 0x4 port1_sd1_OBVoltage = 0x4 port1_sd2_OBVoltage = 0x4 port1_sd3_OBVoltage = 0x4 port2_sd0_OBVoltage = 0x4 port2_sd1_OBVoltage = 0x4 port2_sd2_OBVoltage = 0x4 port2_sd3_OBVoltage = 0x4 ;;;;; Integer parameter. Values range : 0x0 - 0xf. port1_sd0_OBPreEmpPreAmp = 0xf port1_sd1_OBPreEmpPreAmp = 0xf port1_sd2_OBPreEmpPreAmp = 0xf port1_sd3_OBPreEmpPreAmp = 0xf port2_sd0_OBPreEmpPreAmp = 0xf port2_sd1_OBPreEmpPreAmp = 0xf port2_sd2_OBPreEmpPreAmp = 0xf port2_sd3_OBPreEmpPreAmp = 0xf port1_sd0_OBPreEmpOut = 0x5 port1_sd1_OBPreEmpOut = 0x5 port1_sd2_OBPreEmpOut = 0x5 port1_sd3_OBPreEmpOut = 0x5 port2_sd0_OBPreEmpOut = 0x5 port2_sd1_OBPreEmpOut = 0x5 port2_sd2_OBPreEmpOut = 0x5 port2_sd3_OBPreEmpOut = 0x5 port1_sd0_Equal = 0x6 port1_sd1_Equal = 0x6 port1_sd2_Equal = 0x6 port1_sd3_Equal = 0x6 port2_sd0_Equal = 0x6 port2_sd1_Equal = 0x6 port2_sd2_Equal = 0x6 port2_sd3_Equal = 0x6 port1_sd0_OBPreAmp_ddr = 0xf port1_sd1_OBPreAmp_ddr = 0xf port1_sd2_OBPreAmp_ddr = 0xf port1_sd3_OBPreAmp_ddr = 0xf port2_sd0_OBPreAmp_ddr = 0xf port2_sd1_OBPreAmp_ddr = 0xf port2_sd2_OBPreAmp_ddr = 0xf port2_sd3_OBPreAmp_ddr = 0xf ;;;;; Integer parameter. Values range : 0x1 - 0xf. port1_sd0_OBVoltage_ddr = 0x6 port1_sd1_OBVoltage_ddr = 0x6 port1_sd2_OBVoltage_ddr = 0x6 port1_sd3_OBVoltage_ddr = 0x6 port2_sd0_OBVoltage_ddr = 0x6 port2_sd1_OBVoltage_ddr = 0x6 port2_sd2_OBVoltage_ddr = 0x6 port2_sd3_OBVoltage_ddr = 0x6 ;;;;; Integer parameter. Values range : 0x0 - 0xf. port1_sd0_OBPreEmpPreAmp_ddr = 0xf port1_sd1_OBPreEmpPreAmp_ddr = 0xf port1_sd2_OBPreEmpPreAmp_ddr = 0xf port1_sd3_OBPreEmpPreAmp_ddr = 0xf port2_sd0_OBPreEmpPreAmp_ddr = 0xf port2_sd1_OBPreEmpPreAmp_ddr = 0xf port2_sd2_OBPreEmpPreAmp_ddr = 0xf port2_sd3_OBPreEmpPreAmp_ddr = 0xf port1_sd0_OBPreEmpOut_ddr = 0x2 port1_sd1_OBPreEmpOut_ddr = 0x2 port1_sd2_OBPreEmpOut_ddr = 0x2 port1_sd3_OBPreEmpOut_ddr = 0x2 port2_sd0_OBPreEmpOut_ddr = 0x2 port2_sd1_OBPreEmpOut_ddr = 0x2 port2_sd2_OBPreEmpOut_ddr = 0x2 port2_sd3_OBPreEmpOut_ddr = 0x2 port1_sd0_Equal_ddr = 0x7 port1_sd1_Equal_ddr = 0x7 port1_sd2_Equal_ddr = 0x7 port1_sd3_Equal_ddr = 0x7 port2_sd0_Equal_ddr = 0x7 port2_sd1_Equal_ddr = 0x7 port2_sd2_Equal_ddr = 0x7 port2_sd3_Equal_ddr = 0x7 ;;;;; DDR IB Number of Dynamic Options for SerDes (Auto Negotiation) ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 1 - 8. auto_ddr_tx_options = 1 auto_ddr_rx_options = 1 ;;;;; SerDes dynamic parameters for Auto Negotiation ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 0x0 - 0xf. auto_ddr_option_0.tx_preamp = 0xf auto_ddr_option_1.tx_preamp = 0xf auto_ddr_option_2.tx_preamp = 0xf auto_ddr_option_3.tx_preamp = 0xf auto_ddr_option_4.tx_preamp = 0xf auto_ddr_option_5.tx_preamp = 0xf auto_ddr_option_6.tx_preamp = 0xf auto_ddr_option_7.tx_preamp = 0xf ;;;;; Integer parameter. Values range : 0x1 - 0xf. auto_ddr_option_0.tx_voltage = 0x1 auto_ddr_option_1.tx_voltage = 0x1 auto_ddr_option_2.tx_voltage = 0xa auto_ddr_option_3.tx_voltage = 0x1 auto_ddr_option_4.tx_voltage = 0x3 auto_ddr_option_5.tx_voltage = 0x3 auto_ddr_option_6.tx_voltage = 0x3 auto_ddr_option_7.tx_voltage = 0x3 ;;;;; Integer parameter. Values range : 0x0 - 0xf. auto_ddr_option_0.tx_preemppreamp = 0xf auto_ddr_option_1.tx_preemppreamp = 0xf auto_ddr_option_2.tx_preemppreamp = 0xf auto_ddr_option_3.tx_preemppreamp = 0xf auto_ddr_option_4.tx_preemppreamp = 0xf auto_ddr_option_5.tx_preemppreamp = 0xf auto_ddr_option_6.tx_preemppreamp = 0xf auto_ddr_option_7.tx_preemppreamp = 0xf auto_ddr_option_0.tx_preempout = 0x1 auto_ddr_option_1.tx_preempout = 0x1 auto_ddr_option_2.tx_preempout = 0x1 auto_ddr_option_3.tx_preempout = 0x3 auto_ddr_option_4.tx_preempout = 0x3 auto_ddr_option_5.tx_preempout = 0x3 auto_ddr_option_6.tx_preempout = 0x3 auto_ddr_option_7.tx_preempout = 0x3 auto_ddr_option_0.rx_equalization = 0x6 auto_ddr_option_1.rx_equalization = 0x2 auto_ddr_option_2.rx_equalization = 0x5 auto_ddr_option_3.rx_equalization = 0x3 auto_ddr_option_4.rx_equalization = 0x3 auto_ddr_option_5.rx_equalization = 0x3 auto_ddr_option_6.rx_equalization = 0x3 auto_ddr_option_7.rx_equalization = 0x3 ;;;;; e1clk divider to read pll boot record ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0x0 - 0xff. flash_i2c_clk = 0x40 ;;;;; pll divider. i1clk will be e1clk * (m/2n). 0x0 encoding is 16 for m, 8 for n. ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 7. core_n = 2 ;;;;; Integer parameter. Values range : 0 - 15. core_m = 13 ;;;;; When set, the DMU clock freq is not verified at boot time. Longest CAS latency is taken... ;;;;; Under [PLL] section ;;;;; Boolean parameter. Possible values: true, false . ignore_clock_cycle_violation = false ;;;;; pll divider. d1clk will be (1+dmu_deskew) * mclkin * (m/(2-dddso)n) ..... dddso = disable_dmu_divider strapping option ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 7. dmu_n = 4 ;;;;; Integer parameter. Values range : 0 - 15. dmu_m = 8 ;;;;; deskew option to the pll ;;;;; Under [PLL] section ;;;;; Boolean parameter. Possible values: true, false . dmu_deskew = true ;;;;; IB clock divider, for VRCLKP/N pin. ;;;;; for serdes at 2.5Ghz ,the following frequences are allowed for VRCLKP/N input: ;;;;; if input 125MHz put 0x0, ;;;;; 250Mhz put 0x1, ;;;;; 62.5MHz put 0x2, ;;;;; 31.25MHz put 0x3, ;;;;; 100MHz put 0x4-0x7 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 15. r0_ldiv = 2 ;;;;; PCI Express clock divider, for XRCLKP/N. ;;;;; for serdes at 2.5Ghz ,the following frequences are allowed for XRCLKP/N input: ;;;;; if input 125MHz put 0x0, ;;;;; 250Mhz put 0x1, ;;;;; 62.5MHz put 0x2, ;;;;; 31.25MHz put 0x3, ;;;;; 100MHz put 0x4-0x7 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 15. t0_ldiv = 7 ;;;;; (1024 * pll_stabilize) is num of e1clk cycles to wait for stabilization put 1.0 milisec = 1024 * 60 * e1clk(66MHz) . lets put 0x80 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 255. pll_stabilize = 128 ;;;;; VDDIO is higher than 1.2 Volts. ;;;;; Under [PLL] section ;;;;; Boolean parameter. Possible values: true, false . vddio_higher_than_1dot2 = true ;;;;; Input core clock to PLL (KHz) ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 200000. adapter_core_ref_clock_khz = 62500 ;;;;; Input DDR Memory clock to PLL (KHz) ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 200000. adapter_dmu_ref_clock_khz = 62500 ;;;;; Select if disable_dmu_divider strapping option [sdostrb] is set. ;;;;; Under [PLL] section ;;;;; Boolean parameter. Possible values: true, false . disable_dmu_divider = false ;;;;; If set, Output buffers will operate as SSTL1, otherwise as SSTL2 ;;;;; Under [DDR] section ;;;;; Boolean parameter. Possible values: true, false . weak_output_buffers = true weak_output_dqsm = false weak_output_addra = false weak_output_addrb = false weak_output_cmda = false weak_output_cmdb = false weak_output_clkouta = false weak_output_clkoutb = false weak_output_cs = false *************************************************************************************************************************** Table 2: Critical Configuration Parameters for the Tiger/Cheetah family (P/N: MHES14..., MHES18..., MHGS18...) PCI-Ex Cards *************************************************************************************************************************** ;;;;;;; SerDes static parameters for OnlyDDR ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 0x0 - 0xf. port1_sd0_OBPreAmp = 0xf port1_sd1_OBPreAmp = 0xf port1_sd2_OBPreAmp = 0xf port1_sd3_OBPreAmp = 0xf port1_sd0_OBVoltage = 0x4 port1_sd1_OBVoltage = 0x4 port1_sd2_OBVoltage = 0x4 port1_sd3_OBVoltage = 0x4 port1_sd0_OBPreEmpPreAmp = 0xf port1_sd1_OBPreEmpPreAmp = 0xf port1_sd2_OBPreEmpPreAmp = 0xf port1_sd3_OBPreEmpPreAmp = 0xf port1_sd0_OBPreEmpOut = 0x5 port1_sd1_OBPreEmpOut = 0x5 port1_sd2_OBPreEmpOut = 0x5 port1_sd3_OBPreEmpOut = 0x5 port1_sd0_Equal = 0x6 port1_sd1_Equal = 0x6 port1_sd2_Equal = 0x6 port1_sd3_Equal = 0x6 port1_sd0_OBPreAmp_ddr = 0xf port1_sd1_OBPreAmp_ddr = 0xf port1_sd2_OBPreAmp_ddr = 0xf port1_sd3_OBPreAmp_ddr = 0xf port1_sd0_OBVoltage_ddr = 0x6 port1_sd1_OBVoltage_ddr = 0x6 port1_sd2_OBVoltage_ddr = 0x6 port1_sd3_OBVoltage_ddr = 0x6 port1_sd0_OBPreEmpPreAmp_ddr = 0xf port1_sd1_OBPreEmpPreAmp_ddr = 0xf port1_sd2_OBPreEmpPreAmp_ddr = 0xf port1_sd3_OBPreEmpPreAmp_ddr = 0xf port1_sd0_OBPreEmpOut_ddr = 0x2 port1_sd1_OBPreEmpOut_ddr = 0x2 port1_sd2_OBPreEmpOut_ddr = 0x2 port1_sd3_OBPreEmpOut_ddr = 0x2 port1_sd0_Equal_ddr = 0x7 port1_sd1_Equal_ddr = 0x7 port1_sd2_Equal_ddr = 0x7 port1_sd3_Equal_ddr = 0x7 ;;;;; DDR IB Number of Dynamic Options for SerDes (Auto Negotiation) ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 1 - 8. auto_ddr_tx_options = 1 auto_ddr_rx_options = 1 ;;;;; SerDes dynamic parameters for Auto Negotiation ;;;;; Under [IB] section ;;;;; Integer parameter. Values range : 0x0 - 0xf. auto_ddr_option_0.tx_preamp = 0xf auto_ddr_option_1.tx_preamp = 0xf auto_ddr_option_2.tx_preamp = 0xf auto_ddr_option_3.tx_preamp = 0xf auto_ddr_option_4.tx_preamp = 0xf auto_ddr_option_5.tx_preamp = 0xf auto_ddr_option_6.tx_preamp = 0xf auto_ddr_option_7.tx_preamp = 0xf auto_ddr_option_0.tx_voltage = 0x1 auto_ddr_option_1.tx_voltage = 0x1 auto_ddr_option_2.tx_voltage = 0xa auto_ddr_option_3.tx_voltage = 0x1 auto_ddr_option_4.tx_voltage = 0x3 auto_ddr_option_5.tx_voltage = 0x3 auto_ddr_option_6.tx_voltage = 0x3 auto_ddr_option_7.tx_voltage = 0x3 auto_ddr_option_0.tx_preemppreamp = 0xf auto_ddr_option_1.tx_preemppreamp = 0xf auto_ddr_option_2.tx_preemppreamp = 0xf auto_ddr_option_3.tx_preemppreamp = 0xf auto_ddr_option_4.tx_preemppreamp = 0xf auto_ddr_option_5.tx_preemppreamp = 0xf auto_ddr_option_6.tx_preemppreamp = 0xf auto_ddr_option_7.tx_preemppreamp = 0xf auto_ddr_option_0.tx_preempout = 0x1 auto_ddr_option_1.tx_preempout = 0x1 auto_ddr_option_2.tx_preempout = 0x1 auto_ddr_option_3.tx_preempout = 0x3 auto_ddr_option_4.tx_preempout = 0x3 auto_ddr_option_5.tx_preempout = 0x3 auto_ddr_option_6.tx_preempout = 0x3 auto_ddr_option_7.tx_preempout = 0x3 auto_ddr_option_0.rx_equalization = 0x6 auto_ddr_option_1.rx_equalization = 0x2 auto_ddr_option_2.rx_equalization = 0x5 auto_ddr_option_3.rx_equalization = 0x3 auto_ddr_option_4.rx_equalization = 0x3 auto_ddr_option_5.rx_equalization = 0x3 auto_ddr_option_6.rx_equalization = 0x3 auto_ddr_option_7.rx_equalization = 0x3 ;;;;; e1clk divider to read pll boot record ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0x0 - 0xff. flash_i2c_clk = 0x7f ;;;;; pll divider. i1clk will be e1clk * (m/2n). 0x0 encoding is 16 for m, 8 for n. ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 7. core_n = 1 ;;;;; Integer parameter. Values range : 0 - 15. core_m = 6 ;;;;; IB clock divider, for VRCLKP/N pin. ;;;;; for serdes at 2.5Ghz ,the following frequences are allowed for VRCLKP/N input: ;;;;; if input 125MHz put 0x0, ;;;;; 250Mhz put 0x1, ;;;;; 62.5MHz put 0x2, ;;;;; 31.25MHz put 0x3, ;;;;; 100MHz put 0x4-0x7 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 15. r0_ldiv = 2 ;;;;; PCI Express clock divider, for XRCLKP/N. ;;;;; for serdes at 2.5Ghz ,the following frequences are allowed for XRCLKP/N input: ;;;;; if input 125MHz put 0x0, ;;;;; 250Mhz put 0x1, ;;;;; 62.5MHz put 0x2, ;;;;; 31.25MHz put 0x3, ;;;;; 100MHz put 0x4-0x7 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 15. t0_ldiv = 7 ;;;;; (1024 * pll_stabilize) is num of e1clk cycles to wait for stabilization put 1.0 milisec = 1024 * 60 * e1clk(66MHz) . lets put 0x80 ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 255. pll_stabilize = 196 ;;;;; Input core clock to PLL (KHz) ;;;;; Under [PLL] section ;;;;; Integer parameter. Values range : 0 - 200000. adapter_core_ref_clock_khz = 62500
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