------- Additional Comments From bjoern dot m dot haase at web dot de
2005-09-05 06:59 -------
IMO, one would not be able to handle the issue by changing CSE. E.g. I
presently don't see how to avoid using register notes for the following
situation. Imagine a target not having DImode operations so that DImode
arithmetic needs to be lowered to a sequence of SImode operations. Imagine
further that after the sequence the condition code contains useful information
that we want to re-use.
E.g a minus:DI operation would be expanded into two parallels like
(parallel[
(set (subreg:SI (reg:DI operand0) 0)
minus:SI ((subreg:SI (reg:DI operand1) 0)
(subreg:SI (reg:DI operand2) 0))))
(set (reg:CCmode CC) (generate borrow))])
(parallel[
(set (subreg:SI (reg:DI operand0) 4)
minus:SI (
(extract_borrow:SI (reg:CCmode CC))
(minus:SI ((subreg:SI (reg:DI operand1) 4)
(subreg:SI (reg:DI operand2) 4)))))
(set (reg:CCmode CC) (generate condition code))])
In order to describe what information is written to the CC register in the
second parallel, one needs to refer to both, input parameters of the parallel
for the lower 4 bytes and input parameters for the higher 4 bytes. E.g. the
information that CC contains the result of a compare of operand1 and operand2
could therefore not be expressed in the RTL! One could add, however, a third
instruction to the expanded sequence reading
(set (reg:CCmode CC) (reg:CCmode CC))
-> WITH ATTACHED REGISTER NOTE "is equal to compare:DI (operand1) (operand2)"
where the REG_EQUAL note gives the required information. IMO this is a general
issue relevant for all targets that are aiming to do subreg lowering of
arithmetic and logic operations at expand and that wish to recycle the
condition codes generated. Of course 8 bit targets like AVR that need to use
subreg lowering for almost everything will benefit most :-).
I agree that generally register notes are kind of ugly. But for this kind of
information, I think that they could be useful.
Yours,
Bjoern
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23726
