------- Comment #2 from tehila at il dot ibm dot com 2007-07-26 10:46 ------- (In reply to comment #2) Just want a clarification: I see you're compiling on PPU (since you're using -maltivec). Does this problematic also on SPU? Does SPU has this LHS hazard?
Another question: lwz r0,-20(r1) <---- LHS hazard stw r0,lo16(_e)(r2) The problem here is these 2 insns, right? The store that is right after (or too close to) the load ? -- tehila at il dot ibm dot com changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |tehila at il dot ibm dot com http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32826