------- Comment #3 from jakub at gcc dot gnu dot org 2008-11-03 08:14 ------- Isn't this just a user error though? I mean, for -mavx we also need an assembler that supports AVX instructions, we don't have a workaround for every AVX instruction. Even if you build with -march=native on SSSE3 capable CPU (i.e. core2 or later) GCC assumes your assembler supports SSSE3. Similarly for many other recently added instructions. lvlx insn is guarded with rs6000_cpu == PROCESSOR_CELL, how that got set? Are you configuring gcc with a cell arch eventhough your assembler lacks that support? Or is testing done with those flags?
-- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37812
