------- Comment #7 from hjl dot tools at gmail dot com 2008-11-28 22:28 -------
(In reply to comment #6)
> I think, H.J., that is one more latent bug (i already saw several of them) in
> reload inheritance optimization triggered by IRA which allocates dx for p69
> and
> p87 in subsequent insns
>
> 47:p65<-p69
> 151:p87<-mem[...].
>
With my patch, I got
(insn 47 46 151 3 /tmp/foo.f90:53 (set (mem/c:SI (plus:SI (reg/f:SI 6 bp)
(const_int -48 [0xffffffffffffffd0])) [0 %sfp+-24 S4 A32])
(reg:SI 1 dx [orig:69 S.10 ] [69])) 47 {*movsi_1} (nil))
(insn 151 47 48 3 /tmp/foo.f90:6 (set (reg:SI 1 dx [87])
(reg:SI 2 cx [80])) 47 {*movsi_1} (expr_list:REG_EQUIV (mem/u/c:SI
(const:SI (unspec:SI [
(symbol_ref:SI ("__threadprivate2_MOD_foo") [flags
0x60] <var_decl 0x7fad44900780 foo>)
] 8)) [0 S4 A8])
(nil)))
(insn 48 151 167 3 /tmp/foo.f90:6 (set (reg:SI 1 dx)
(mem/s/j:SI (plus:SI (plus:SI (unspec:SI [
(const_int 0 [0x0])
] 18)
(reg:SI 1 dx [87]))
(const_int 24 [0x18])) [0 <variable>.stride+0 S4 A32])) 47
{*movsi_1} (nil))
(insn 167 48 168 3 /tmp/foo.f90:6 (set (mem/c:SI (plus:SI (reg/f:SI 6 bp)
(const_int -56 [0xffffffffffffffc8])) [0 %sfp+-32 S4 A32])
(reg:SI 1 dx)) 47 {*movsi_1} (nil))
(insn 168 167 49 3 /tmp/foo.f90:6 (set (reg:SI 1 dx [orig:62 D.2019 ] [62])
(mem/c:SI (plus:SI (reg/f:SI 6 bp)
(const_int -56 [0xffffffffffffffc8])) [0 %sfp+-32 S4 A32])) 47
{*movsi_1} (nil))
(insn 49 168 50 3 /tmp/foo.f90:6 (parallel [
(set (reg:SI 1 dx [orig:62 D.2019 ] [62])
(mult:SI (reg:SI 1 dx [orig:62 D.2019 ] [62])
(mem/c:SI (plus:SI (reg/f:SI 6 bp)
(const_int -48 [0xffffffffffffffd0])) [0 %sfp+-24
S4 A32])))
(clobber (reg:CC 17 flags))
]) 333 {*mulsi3_1} (nil))
DX (r69) is dead at insn 47. DX (r87) at insn 151 is a different register.
It looks OK to me.
> I am not sure that your patch is right but you can commit it for a review to
> get some comments.
>
I will submit it for comments after I finish tests on Linux/ia32, Linux/ia64
and Linux/Intel64.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38272
