------- Comment #4 from amylaar at gcc dot gnu dot org 2009-03-02 18:59 ------- (In reply to comment #3) > I still don't understand what you mean by that. Do you mean the registers are > vector based and the instructions effect the conditional register and that > conditional register has slots (elements) that correspond to the vector slots > (elements)?
Exactly. The conditiona register is known as V8CCImode for ordinary integer instructions, V8CCZNmode if only N/Z flags matter, and V8CCZmode when only the Z falg is relevant. You can copy it from/to a general purpose vector register, in which case it looks like a V8PHImode register with 6 valid bits per element. There are also use cases where it acts as having 32 bit partial elements. > Still having a vector mode of CCmode seems weird. Actually, it makes more sense than a scalar CCmode register. The limited clock frequency is compensated for by higher throughput per cycle. Van Neumann would have said that having a processor with 4 or 5 different types of physical memory (L1 Dcache, L1 Icache, L2 cache, maybe L3 cache, main memory) seems weird. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39347