Moving this issue from bz 39976 since it is a separate problem than the original documented there.
Verified the behavior still exists using current trunk revision (150020). The testcase comes from cpu2000 sixtrack benchmark. Following is original comment I posted: ======= The attatched testcase exhibits the problem with the load-hit-store. It's resulting from choosing a bad register class (GENERAL_REGS) for a pseudo that should get assigned to FLOAT_REGS. Since there is no FPR -> GPR move for -mcpu=power6 the copy must go through memory. I compiled the testcase with -m64 -O3 -mcpu=power6 using trunk revision 149376. The pseudo in question is 361. Following are the 3 insns referencing reg 361 in the sched1 dump (before ira): (insn 51 238 241 8 thin6d_reduced.f:178 (set (reg:DF 361 [ prephitmp.35 ]) (reg:DF 358 [ prephitmp.35 ])) 351 {*movdf_hardfloat64} (nil)) ... (insn 47 46 231 9 thin6d_reduced.f:178 (set (reg:DF 361 [ prephitmp.35 ]) (reg:DF 179 [ prephitmp.35 ])) 351 {*movdf_hardfloat64} (nil)) ... (insn 196 194 198 11 thin6d_reduced.f:169 (set (mem/c/i:DF (plus:DI (reg/f:DI 477) (const_int 56 [0x38])) [2 crkve+0 S8 A64]) (reg:DF 361 [ prephitmp.35 ])) 351 {*movdf_hardfloat64} (expr_list:REG_DEAD (reg:DF 361 [ prephitmp.35 ]) (nil))) And from the ira dump: Pass1 cost computation: a71 (r361,l1) best GENERAL_REGS, cover GENERAL_REGS a3 (r361,l0) best GENERAL_REGS, cover GENERAL_REGS a3(r361,l0) costs: BASE_REGS:0,0 GENERAL_REGS:0,0 FLOAT_REGS:0,0 LINK_REGS:156,1836 CTR_REGS:156,1836 SPECIAL_REGS:156,1836 MEM:156 a71(r361,l1) costs: BASE_REGS:0,0 GENERAL_REGS:0,0 FLOAT_REGS:0,0 LINK_REGS:1680,1680 CTR_REGS:1680,1680 SPECIAL_REGS:1680,1680 MEM:1120 Pass 2 cost computation: r361: preferred GENERAL_REGS, alternative NO_REGS a3(r361,l0) costs: BASE_REGS:0,2240 GENERAL_REGS:0,2240 FLOAT_REGS:312,2552 LINK_REGS:234,4154 CTR_REGS:234,4154 SPECIAL_REGS:234,4154 MEM:156 a71(r361,l1) costs: BASE_REGS:2240,2240 GENERAL_REGS:2240,2240 FLOAT_REGS:2240,2240 LINK_REGS:3920,3920 CTR_REGS:3920,3920 SPECIAL_REGS:3920,3920 MEM:3360 -- Summary: Poor register class choice in IRA Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: pthaugen at gcc dot gnu dot org GCC build triplet: powerpc64*-*-* GCC host triplet: powerpc64*-*-* GCC target triplet: powerpc64*-*-* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40842