Compile the following c++ code with options -march=armv7-a -mthumb -Os struct A { bool v:1; };
bool bar(); bool foo(struct A* p) { if (p->v) return true; return bar(); } Gcc generates _Z3fooP1A: push {r3, lr} .save {r3, lr} .LCFI0: ldrb r3, [r0, #0] @ zero_extendqisi2 tst r3, #1 bne .L3 bl _Z3barv b .L2 .L3: movs r0, #1 .L2: pop {r3, pc} The "tst r3, #1" is a 32 bit instruction, it can be replaced by a 16 bit instruction "lsl r3, r3, 31" while still retain the original semantics. -- Summary: Replace "tst r3, 1" with "lsl r3, r3, 31" in thumb2 Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: carrot at google dot com GCC build triplet: i686-linux GCC host triplet: i686-linux GCC target triplet: arm-eabi http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42879