------- Comment #5 from ubizjak at gmail dot com 2010-05-08 11:19 -------
(In reply to comment #4)
> Uros your proposed patch seems to cause:
>
> /src/gcc-4.5.0/libgcc/../gcc/libgcc2.c: In function '__negti2':
> /src/gcc-4.5.0/libgcc/../gcc/libgcc2.c:76:1: error: insn does not satisfy its
> constraints:
> (insn 31 16 20 2 /src/gcc-4.5.0/libgcc/../gcc/libgcc2.c:75 (set (mem/c/i:TI
> (reg/f:DI 16 $16 [orig:78 D.3782 ] [78]) [6 <retval>+0 S16 A128])
> (reg:TI 22 $22)) 228 {*movti_internal} (nil))
This pattern expects "offsetable" memory operand, and substituting SImode
addition with a temporary register violates this requirement. As noted
elsewhere [1],
<quote>
I suppose you have hit a 32/64 pointer issue. This requires some
investigation! We plan to fix them, but we haven't yet started this work on
gcc 4.5
</quote>
Since HW pointers are 64bit wide, and OS uses 32bit pointers, it looks to me
that "offsetable" addresses are invalid, since they can't be substituted with
teporary register. However, the precise details of VMS (address wrapping and
similar issues) are not known to me, so I can't say for sure.
Anyway, operands with "address_operand" predicate are processed as if they were
always in DImode (see unaligned_* patterns in alpha.md), which is not the case
with 32bit pointers. This leads to invalid RTXes with mixed-up modes, see
Comment #2.
[1] http://gcc.gnu.org/ml/gcc/2010-05/msg00030.html
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43973
