Compile the following code with options -march=armv7-a -mthumb -Os

int bar5(int x)
{
  if (x == -1)
    return 3;
  return 5;
}

GCC generates

        cmp     r0, #-1   // A
        ite     ne
        movne   r0, #5
        moveq   r0, #3
        bx      lr

If we replace instruction A with 'add  r0, 1', it has the same effect, but with
smaller code size. Because cmp with negative immediate instruction is 32 bit.
Add with small positive immediate instruction is 16 bit.

In thumb1 we already have insn cbranchsi4_scratch to do this, we need a similar
part in thumb2.


-- 
           Summary: Use 'add r0, 1' to replace 'cmp r0, -1' in thumb2
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: carrot at google dot com
 GCC build triplet: i686-linux
  GCC host triplet: i686-linux
GCC target triplet: arm-eabi


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44072

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