Compile the following code with options -march=armv7-a -mthumb -Os

int tp(int x, int y)
{
  return (x & 0xff) - (y & 0xffff);
}

GCC generates:

        uxth    r1, r1
        and     r0, r0, #255   //A
        subs    r0, r0, r1
        bx      lr

Instruction A is 32 bit, it can be replace by uxtb, a 16 bit equivalent
instruction.

A possible implementation is to call gen_thumb2_zero_extendqisi2_v6 in pattern
(define_expand "andsi3").


-- 
           Summary: "and r0, r0, #255" can be replace with uxtb in thumb2
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: carrot at google dot com
 GCC build triplet: i686-linux
  GCC host triplet: i686-linux
GCC target triplet: arm-eabi


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44999

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