Compile the following code with options -march=armv7-a -mthumb -O2 -fpic
struct S
{
void* p1;
void* p2;
void* p3;
void* p4;
};
void foo1(struct S* fp, struct S* otherSaveArea)
{
struct S* saveArea = fp - 1;
printf("StackSaveArea for fp %p [%p/%p]:\n", fp, saveArea, otherSaveArea);
printf(" prevFrame=%p savedPc=%p meth=%p curPc=%p fp[0]=0x%08x\n",
saveArea->p1, saveArea->p2,saveArea->p3,saveArea->p4,*(unsigned
int*)fp);
}
GCC 4.6 generates
foo1:
push {r4, r5, r6, lr}
mov r4, r0
ldr r5, .L2
sub sp, sp, #8
mov r3, r1
sub r2, r0, #16
.LPIC0:
add r5, pc
mov r1, r0
mov r0, r5
bl printf(PLT)
ldr r6, [r4, #-4] // A
ldr r5, [r4, #0] // B
ldr r0, .L2+4
ldr r1, [r4, #-16] // C
ldr r2, [r4, #-12] // D
.LPIC1:
add r0, pc
ldr r3, [r4, #-8]
str r6, [sp, #0] // E
str r5, [sp, #4] // F
bl printf(PLT)
add sp, sp, #8
pop {r4, r5, r6, pc}
Notice instructions A and B loading two consecutive words, they can be written
as a single instruction
ldrd r6, r5, [r4, -4]
It results in shorter and potentially faster code. Similarly instructions C and
D can be replace by a ldrd. Instructions E and F shows a chance for strd
instruction.
We don't have a ldrd insn pattern to represent two separate loads. Maybe we can
define one and let combine to find the chances.
There is also the same opportunity for ARM instructions, but there are more
constraints on register usage. In arm mode, the first register must be even
numbered and the second register number must be exact successor of the first
one. These are similar to the constraints of ldm and stm, and our register
allocator can't handle them.
--
Summary: Use ldrd to load two consecutive words
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45335
