http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48974
Summary: VIS intrinsics improvement opportunities
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: enhancement
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: h...@gcc.gnu.org
Target: sparc64-*-*
While writing a VIS backend for RAPP,
http://savannah.nongnu.org/projects/rapp/ using gcc54 at the compilefarm I
noticed a few omissions and opportunities for improvements. I just thought
adding some notes here would be better than nothing, before I forget.
1. The insns fone / fones are unused (in contrast to fzero / fzeros).
2. The implicit dependency on the GSR control register from the fpack* and
faligndata insns aren't expressed in the intrinsics. There's also no way to set
GSR other than through an asm (or by __builtin_vis_alignaddr, for the
side-effect of setting the GSR.alignaddr_offset field). This makes those
intrinsics next to useless compared to naked asms. An intuitive way to set GSR
for those intrinsics would be as a parameter to the fpack* and faligndata
intrinsics (or rather, new variants), and generating a CSE:able setting of GSR
when expanding the intrinsic (and changing the __builtin_vis_alignaddr to be a
parallel, setting the same pseudo or just clobbering it). See the
initial-value machinery and its use in various ports for managing a suitable
pseudo for a hard-register; get_hard_reg_initial_val and friends.
