http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50088
--- Comment #14 from H.J. Lu <hjl.tools at gmail dot com> 2011-08-17 13:37:39 UTC --- (In reply to comment #13) > (In reply to comment #12) > > Created attachment 25025 [details] > > A patch to use the same mode for shift count > > > > This is an untested patch to use the same mode for shift count. > > We should find solution for the general problem. Not for its specific > appearance in reproducer. > > We may have the same issue for any other instructions consuming byte register > and it is better to fix the source of the problem (which is I suppose in IRA) > and do not introduce workaround for each such instruction. I think this problem is unique to x86 since some instructions have different sizes in register operands. In this example, shift count is CL regardless the source operand size. I am not sure how much RA can help here. By making register operands in shift instructions to have the same size (32bit or less), it may work for most cases. > BTW I think you should not increase size of immediate operands in your patch. My patch is totally untested and probably is wrong.