http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50749
Bug #: 50749
Summary: SH Target: Post-increment addressing used only for
first memory access
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: oleg.e...@t-online.de
CC: kkoj...@gcc.gnu.org
Target: sh*-*-*
Post-increment addressing is generated only for the first
memory access. Any subsequent memory access does not use
post-increment addressing.
The following two functions are reduced examples and result
in the same code being generated.
The problem exists with any number of memory accesses > 1
and at any optimization level.
int test_0 (char* p, int c)
{
int r = 0;
r += *p++;
r += *p++;
r += *p++;
return r;
}
int test_1 (char* p, int c)
{
int r = 0;
r += p[0];
r += p[1];
r += p[2];
return r;
}
compiled with -fno-ivopts -Os -m4-single -ml ...
mov r4,r1
mov.b @r1+,r0
add #2,r4
mov.b @r1,r1
add r1,r0
mov.b @r4,r1
rts
add r1,r0
This could be done better ...
mov.b @r4+,r0
mov.b @r4+,r1
add r1,r0
mov.b @r4+,r1
rts
add r1,r0
Another example with a loop:
int test_func_1 (char* p, int c)
{
int r = 0;
do
{
r += *p++;
r += *p++;
} while (--c);
return r;
}
compiled with -fno-ivopts -Os -m4-single -ml ...
mov #0,r0
.L5:
mov r4,r1
mov.b @r1+,r2
dt r5
mov.b @r1,r1
add r2,r0
add #2,r4
bf/s .L5
add r1,r0
rts
nop
would be better as:
mov #0, r0
.L5:
mov.b @r4+, r1
dt r5
mov.b @r4+, r2
add r1, r0
bf/s .L5
add r2, r0
rts
nop
Using built-in specs.
COLLECT_GCC=sh-elf-gcc
COLLECT_LTO_WRAPPER=/usr/local/libexec/gcc/sh-elf/4.7.0/lto-wrapper
Target: sh-elf
Configured with: ../gcc-trunk/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp --disable-nls
--disable-werror --enable-lto --with-newlib --with-gnu-as --with-gnu-ld
--with-system-zlib
Thread model: single
gcc version 4.7.0 20111016 (experimental) (GCC)
