http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53358
Bug #: 53358
Summary: [4.7/4.8 Regression] ICE due to
TARGET_READ_MODIFY_WRITE peephole2
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
Priority: P3
Component: target
AssignedTo: ja...@gcc.gnu.org
ReportedBy: ja...@gcc.gnu.org
Target: i?86-*
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-additional-options "-fpic" { target fpic } } */
/* { dg-additional-options "-mtune=pentium4" { target { { i?86-*-* x86_64-*-* }
&& ia32 } } } */
struct S { unsigned char s, t[17]; };
int bar (void);
void
foo (struct S *x)
{
unsigned char i, z;
if (bar ())
{
z = bar ();
bar ();
x->s += z;
for (i = 0; i < x->s; i++)
x->t[i] = bar ();
}
}
ICEs with:
rh821223.i: In function 'foo':
rh821223.i:21:1: error: insn does not satisfy its constraints:
(insn 77 22 27 3 (parallel [
(set (reg:CCZ 17 flags)
(compare:CCZ (plus:QI (mem:QI (reg/v/f:SI 4 si [orig:72 x ]
[72]) [0 x_5(D)->s+0 S1 A8])
(reg:QI 5 di [orig:63 D.1372 ] [63]))
(const_int 0 [0])))
(set (mem:QI (reg/v/f:SI 4 si [orig:72 x ] [72]) [0 x_5(D)->s+0 S1
A8])
(plus:QI (mem:QI (reg/v/f:SI 4 si [orig:72 x ] [72]) [0
x_5(D)->s+0 S1 A8])
(reg:QI 5 di [orig:63 D.1372 ] [63])))
]) rh821223.i:18 259 {*addqi_2}
(nil))
rh821223.i:21:1: internal compiler error: in copyprop_hardreg_forward_1, at
regcprop.c:767
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://gcc.gnu.org/bugs.html> for instructions.
The problem is that addqi_1 pattern before the peephole2 in some alternatives
allows "r" registers rather than "q" and emits addl instead of addq in that
case, and the peepholes I've added for 4.7+ didn't think about such a
possibility.
