http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #4 from Marc Glisse <glisse at gcc dot gnu.org> 2012-10-12 17:33:53 UTC --- Note that a V4SF version should be doable, since it is 3 insn there as well, although the pattern is different. (insn 34 61 36 4 (set (reg:SF 103 [ D.2551 ]) (vec_select:SF (reg/v:V4SF 87 [ v ]) (parallel [ (const_int 0 [0]) ]))) d.c:13 1380 {*vec_extractv4sf_0} (nil)) (insn 36 34 37 4 (set (reg:SF 104 [ D.2551 ]) (minus:SF (reg:SF 103 [ D.2551 ]) (reg:SF 106))) d.c:13 759 {*fop_sf_1_sse} (expr_list:REG_DEAD (reg:SF 103 [ D.2551 ]) (nil))) (insn 37 36 38 4 (set (reg/v:V4SF 87 [ v ]) (vec_merge:V4SF (vec_duplicate:V4SF (reg:SF 104 [ D.2551 ])) (reg/v:V4SF 87 [ v ]) (const_int 1 [0x1]))) d.c:13 1377 {vec_setv4sf_0} (expr_list:REG_DEAD (reg:SF 104 [ D.2551 ]) (nil)))