http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55571
Jakub Jelinek <jakub at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org --- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-12-03 13:54:57 UTC --- Perhaps just guard the PR48076 changes with #if defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) \ || defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) and otherwise just use asm volatile ("" : : : "memory"); barrier? Or for those targets avoid the optimization: #if defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) \ || defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) # define USE_ATOMICS #endif #ifdef USE_ATOMICS pointer offset = __atomic_load_n (&obj->loc.offset, __ATOMIC_ACQUIRE); #else pointer offset = 0; #endif if (__builtin_expect (offset == 0, 0)) ... #ifdef USE_ATOMICS __atomic_store_n (&obj->loc.offset, offset, __ATOMIC_RELEASE); #else obj->loc.offset = offset; #endif Then for the targets without sync compare and swap it will always grab the lock and do everything with the lock held.