http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39469
--- Comment #6 from Siarhei Siamashka <siarhei.siamashka at gmail dot com> 2012-12-10 00:24:12 UTC --- (In reply to comment #5) > (In reply to comment #4) > > The ARM backend should do a splitter just like the rs6000 back-end does if > > it > > is faster/smaller to load a constant via the instructions. > > I'm not sure if rs6000 is any better. It looks just as bad as ARM, based on my > experience trying to optimize > http://lists.freedesktop.org/archives/pixman/2012-December/002394.html And the testcase attached to this bug compiles to the following code with powerpc-unknown-linux-gnu-gcc (-O2 optimizations): .file "test.c" .section ".text" .align 2 .globl foo .type foo, @function foo: lis 8,0x5f5 lis 10,array@ha ori 8,8,57600 la 9,array@l(10) stw 8,array@l(10) lis 10,0xbeb ori 10,10,49664 stw 10,4(9) lis 10,0x17d7 ori 10,10,33792 stw 10,8(9) lis 10,0x2faf ori 10,10,2048 stw 10,12(9) blr .size foo, .-foo .align 2 .globl bar .type bar, @function bar: lis 10,array@ha slwi 6,3,1 la 9,array@l(10) slwi 7,3,2 slwi 8,3,3 stw 3,array@l(10) stw 6,4(9) stw 7,8(9) stw 8,12(9) blr .size bar, .-bar .ident "GCC: (GNU) 4.8.0 20121209 (experimental)" .section .note.GNU-stack,"",@progbits That's 15 instructions in "foo" vs. 10 in "bar". For MIPS the difference is 16 instructions vs. 11 (I'm not posting the code because it is rather similar). Is this really an ARM target bug?
