http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55882
Bug #: 55882
Summary: unaligned load/store : incorrect struct offset
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: jan.sm...@alcatel-lucent.com
void testfunction(somestruct * chip)
{
unsigned i;
for (i = 0; i < 4; i++)
{
{
tUint64 mask = ((((((((((chip->pp_mask) & (0x00200000)) ? (0x08) :
(((chip->pp_mask) & (0x00000200)) ? (0x0C) : 0xDEADBEEF))))-1) - (0) +
1)==64)?0ull:((1ull)<<((((((((((chip->pp_mask) & (0x00200000)) ? (0x08) :
(((chip->pp_mask) & (0x00000200)) ? (0x0C) : 0xDEADBEEF))))-1) - (0) + 1) <
(63)) ? (((((((chip->pp_mask) & (0x00200000)) ? (0x08) : (((chip->pp_mask) &
(0x00000200)) ? (0x0C) : 0xDEADBEEF))))-1) - (0) + 1) : (63))))) - 1) << ((1) ?
(0) : ((((((chip->pp_mask) & (0x00200000)) ? (0x08) : (((chip->pp_mask) &
(0x00000200)) ? (0x0C) : 0xDEADBEEF)))) - 1 - ((((((chip->pp_mask) &
(0x00200000)) ? (0x08) : (((chip->pp_mask) & (0x00000200)) ? (0x0C) :
0xDEADBEEF))))-1)));
chip->config->smth[i].xyz = chip->config->smth[i].xyz & ~mask;
};
}
The structure 'somestruct' is hard to reduce and for various reasons I can not
disclose it.
GCC 4.6 :
=========
00000000 <testfunction>:
0: 27bdffe8 addiu sp,sp,-24
4: afbe0014 sw s8,20(sp)
8: 03a0f02d move s8,sp
c: afc40018 sw a0,24(s8)
10: afc00000 sw zero,0(s8)
14: 08000059 j 164 <testfunction+0x164>
18: 00000000 nop
1c: 8fc20018 lw v0,24(s8)
20: 8c431ab8 lw v1,6840(v0)
24: 3c020020 lui v0,0x20
28: 00621024 and v0,v1,v0
2c: 14400006 bnez v0,48 <testfunction+0x48>
30: 00000000 nop
34: 8fc20018 lw v0,24(s8)
38: 8c421ab8 lw v0,6840(v0)
3c: 30420200 andi v0,v0,0x200
40: 10400018 beqz v0,a4 <testfunction+0xa4>
44: 00000000 nop
48: 8fc20018 lw v0,24(s8)
4c: 8c431ab8 lw v1,6840(v0)
50: 3c020020 lui v0,0x20
54: 00621024 and v0,v1,v0
58: 1440000e bnez v0,94 <testfunction+0x94>
5c: 00000000 nop
60: 8fc20018 lw v0,24(s8)
64: 8c421ab8 lw v0,6840(v0)
68: 30420200 andi v0,v0,0x200
6c: 10400005 beqz v0,84 <testfunction+0x84>
70: 00000000 nop
74: 24030fff li v1,4095
78: 0000102d move v0,zero
7c: 08000023 j 8c <testfunction+0x8c>
80: 00000000 nop
84: 2403ffff li v1,-1
88: 2402ffff li v0,-1
8c: 08000027 j 9c <testfunction+0x9c>
90: 00000000 nop
94: 240300ff li v1,255
98: 0000102d move v0,zero
9c: 0800002c j b0 <testfunction+0xb0>
a0: 00000000 nop
a4: 2403ffff li v1,-1
a8: 3c027fff lui v0,0x7fff
ac: 3442ffff ori v0,v0,0xffff
b0: afc3000c sw v1,12(s8)
b4: afc20008 sw v0,8(s8)
b8: 8fc20018 lw v0,24(s8)
bc: 8c461ac0 lw a2,6848(v0)
c0: 8fc20018 lw v0,24(s8)
c4: 8c451ac0 lw a1,6848(v0)
c8: 8fc40000 lw a0,0(s8)
cc: 0080182d move v1,a0
d0: 00031080 sll v0,v1,0x2
d4: 0040182d move v1,v0
d8: 00031080 sll v0,v1,0x2
dc: 00431023 subu v0,v0,v1
e0: 00441023 subu v0,v0,a0
e4: 000211c0 sll v0,v0,0x7
e8: 00a21021 addu v0,a1,v0
ec: 8c4212d0 lw v0,4816(v0)
f0: 00021502 srl v0,v0,0x14
f4: 3042ffff andi v0,v0,0xffff
f8: 0040182d move v1,v0
fc: 97c2000e lhu v0,14(s8)
100: 00021027 nor v0,zero,v0
104: 3042ffff andi v0,v0,0xffff
108: 00621024 and v0,v1,v0
10c: 3042ffff andi v0,v0,0xffff
110: 30420fff andi v0,v0,0xfff
114: 3045ffff andi a1,v0,0xffff
118: 8fc40000 lw a0,0(s8)
11c: 0080182d move v1,a0
120: 00031080 sll v0,v1,0x2
124: 0040182d move v1,v0
128: 00031080 sll v0,v1,0x2
12c: 00431023 subu v0,v0,v1
130: 00441023 subu v0,v0,a0
134: 000211c0 sll v0,v0,0x7
138: 00c21021 addu v0,a2,v0
13c: 00051d00 sll v1,a1,0x14
140: 8c4512d0 lw a1,4816(v0) <<<<< !
144: 3c04000f lui a0,0xf
148: 3484ffff ori a0,a0,0xffff
14c: 00a42024 and a0,a1,a0
150: 00831825 or v1,a0,v1
154: ac4312d0 sw v1,4816(v0) <<<<< !
158: 8fc20000 lw v0,0(s8)
15c: 24420001 addiu v0,v0,1
160: afc20000 sw v0,0(s8)
164: 8fc20000 lw v0,0(s8)
168: 2c420004 sltiu v0,v0,4
16c: 1440ffab bnez v0,1c <testfunction+0x1c>
170: 00000000 nop
174: 03c0e82d move sp,s8
178: 8fbe0014 lw s8,20(sp)
17c: 27bd0018 addiu sp,sp,24
180: 03e00008 jr ra
184: 00000000 nop
GCC 4.8
=======
00000000 <testfunction>:
0: 27bdffe8 addiu sp,sp,-24
4: afbe0014 sw s8,20(sp)
8: 03a0f02d move s8,sp
c: afc40018 sw a0,24(s8)
10: afc00000 sw zero,0(s8)
14: 0800005a j 168 <testfunction+0x168>
18: 00000000 nop
1c: 8fc20018 lw v0,24(s8)
20: 8c431ab8 lw v1,6840(v0)
24: 3c020020 lui v0,0x20
28: 00621024 and v0,v1,v0
2c: 14400006 bnez v0,48 <testfunction+0x48>
30: 00000000 nop
34: 8fc20018 lw v0,24(s8)
38: 8c421ab8 lw v0,6840(v0)
3c: 30420200 andi v0,v0,0x200
40: 10400018 beqz v0,a4 <testfunction+0xa4>
44: 00000000 nop
48: 8fc20018 lw v0,24(s8)
4c: 8c431ab8 lw v1,6840(v0)
50: 3c020020 lui v0,0x20
54: 00621024 and v0,v1,v0
58: 1440000e bnez v0,94 <testfunction+0x94>
5c: 00000000 nop
60: 8fc20018 lw v0,24(s8)
64: 8c421ab8 lw v0,6840(v0)
68: 30420200 andi v0,v0,0x200
6c: 10400005 beqz v0,84 <testfunction+0x84>
70: 00000000 nop
74: 24030fff li v1,4095
78: 0000102d move v0,zero
7c: 08000027 j 9c <testfunction+0x9c>
80: 00000000 nop
84: 2403ffff li v1,-1
88: 2402ffff li v0,-1
8c: 0800002c j b0 <testfunction+0xb0>
90: 00000000 nop
94: 240300ff li v1,255
98: 0000102d move v0,zero
9c: 0800002c j b0 <testfunction+0xb0>
a0: 00000000 nop
a4: 2403ffff li v1,-1
a8: 3c027fff lui v0,0x7fff
ac: 3442ffff ori v0,v0,0xffff
b0: afc3000c sw v1,12(s8)
b4: afc20008 sw v0,8(s8)
b8: 8fc20018 lw v0,24(s8)
bc: 8c461ac0 lw a2,6848(v0)
c0: 8fc20018 lw v0,24(s8)
c4: 8c451ac0 lw a1,6848(v0)
c8: 8fc40000 lw a0,0(s8)
cc: 0080182d move v1,a0
d0: 00031080 sll v0,v1,0x2
d4: 0040182d move v1,v0
d8: 00031080 sll v0,v1,0x2
dc: 00431023 subu v0,v0,v1
e0: 00441023 subu v0,v0,a0
e4: 000211c0 sll v0,v0,0x7
e8: 00a21021 addu v0,a1,v0
ec: 8c4212d0 lw v0,4816(v0)
f0: 00021502 srl v0,v0,0x14
f4: 3042ffff andi v0,v0,0xffff
f8: 0040182d move v1,v0
fc: 97c2000e lhu v0,14(s8)
100: 00021027 nor v0,zero,v0
104: 3042ffff andi v0,v0,0xffff
108: 00621024 and v0,v1,v0
10c: 3042ffff andi v0,v0,0xffff
110: 30420fff andi v0,v0,0xfff
114: 3045ffff andi a1,v0,0xffff
118: 8fc40000 lw a0,0(s8)
11c: 0080182d move v1,a0
120: 00031080 sll v0,v1,0x2
124: 0040182d move v1,v0
128: 00031080 sll v0,v1,0x2
12c: 00431023 subu v0,v0,v1
130: 00441023 subu v0,v0,a0
134: 000211c0 sll v0,v0,0x7
138: 00c21021 addu v0,a2,v0
13c: 30a30fff andi v1,a1,0xfff
140: 00031900 sll v1,v1,0x4
144: 8c4512ce lw a1,4814(v0) <<<<< !
148: 3c04ffff lui a0,0xffff
14c: 3484000f ori a0,a0,0xf
150: 00a42024 and a0,a1,a0
154: 00831825 or v1,a0,v1
158: ac4312ce sw v1,4814(v0) <<<<< !
15c: 8fc20000 lw v0,0(s8)
160: 24420001 addiu v0,v0,1
164: afc20000 sw v0,0(s8)
168: 8fc20000 lw v0,0(s8)
16c: 2c420004 sltiu v0,v0,4
170: 1440ffaa bnez v0,1c <testfunction+0x1c>
174: 00000000 nop
178: 03c0e82d move sp,s8
17c: 8fbe0014 lw s8,20(sp)
180: 27bd0018 addiu sp,sp,24
184: 03e00008 jr ra
188: 00000000 nop
$ diff --side-by-side --suppress-common /tmp/46 /tmp/48 -W120 |less
14: 08000059 j 164 <testfunction+0x164> | 14:
0800005a j 168 <testfunction+0x168>
7c: 08000023 j 8c <testfunction+0x8c> | 7c:
08000027 j 9c <testfunction+0x9c>
8c: 08000027 j 9c <testfunction+0x9c> | 8c:
0800002c j b0 <testfunction+0xb0>
13c: 00051d00 sll v1,a1,0x14 | 13c:
30a30fff andi v1,a1,0xfff
140: 8c4512d0 lw a1,4816(v0) | 140:
00031900 sll v1,v1,0x4
144: 3c04000f lui a0,0xf | 144:
8c4512ce lw a1,4814(v0)
148: 3484ffff ori a0,a0,0xffff | 148:
3c04ffff lui a0,0xffff
14c: 00a42024 and a0,a1,a0 | 14c:
3484000f ori a0,a0,0xf
150: 00831825 or v1,a0,v1 | 150:
00a42024 and a0,a1,a0
154: ac4312d0 sw v1,4816(v0) | 154:
00831825 or v1,a0,v1
158: 8fc20000 lw v0,0(s8) | 158:
ac4312ce sw v1,4814(v0)
15c: 24420001 addiu v0,v0,1 | 15c:
8fc20000 lw v0,0(s8)
160: afc20000 sw v0,0(s8) | 160:
24420001 addiu v0,v0,1
164: 8fc20000 lw v0,0(s8) | 164:
afc20000 sw v0,0(s8)
168: 2c420004 sltiu v0,v0,4 | 168:
8fc20000 lw v0,0(s8)
16c: 1440ffab bnez v0,1c <testfunction+0x1c | 16c:
2c420004 sltiu v0,v0,4
170: 00000000 nop | 170:
1440ffaa bnez v0,1c <testfunction+0x1c
174: 03c0e82d move sp,s8 | 174:
00000000 nop
178: 8fbe0014 lw s8,20(sp) | 178:
03c0e82d move sp,s8
17c: 27bd0018 addiu sp,sp,24 | 17c:
8fbe0014 lw s8,20(sp)
180: 03e00008 jr ra | 180:
27bd0018 addiu sp,sp,24
184: 00000000 nop | 184:
03e00008 jr ra
> 188:
00000000 nop
