http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56439
--- Comment #7 from Chung-Ju Wu <jasonwucj at gmail dot com> 2013-02-26
03:30:40 UTC ---
Sorry I didn't notice that it is 8-bit register on avr.
I was porting a 32-bit register target and this case is similar to mine.
That's why I have such guess in comment 5.
Now I tried to build an avr-elf target and test it with your code fragment,
using following command: $ avr-elf-gcc -S -Os test.c -fdump-rtl-all
Here are my preliminary observation:
As Andrew Pinski said in comment 3, global register variable is treated
as a volatile variable. So have:
$ vi a.c.150r.expand
25 (insn 5 4 6 3 (set (reg:QI 42 [ foo.0 ])
26 (reg/v:QI 4 r4 [ foo ])) a.c:11 -1
27 (nil))
28
29 (insn 6 5 7 3 (set (reg:QI 43 [ foo.1 ])
30 (ashift:QI (reg:QI 42 [ foo.0 ])
31 (const_int 1 [0x1]))) a.c:11 -1
32 (nil))
33
34 (insn 7 6 8 3 (set (reg/v:QI 4 r4 [ foo ])
35 (reg:QI 43 [ foo.1 ])) a.c:11 -1
36 (nil))
37
Then, in the combine phase,
I notice that it does try to combine insn-5 and insn-6.
But it does not further combine insn-6 and insn-7.
$ vi a.c.185r.combine
29 (insn 6 5 7 2 (set (reg:QI 43 [ foo.1 ])
30 (ashift:QI (reg/v:QI 4 r4 [ foo ])
31 (const_int 1 [0x1]))) a.c:11 199 {*ashlqi3}
32 (expr_list:REG_DEAD (reg/v:QI 4 r4 [ foo ])
33 (nil)))
34
35 (insn 7 6 8 2 (set (reg/v:QI 4 r4 [ foo ])
36 (reg:QI 43 [ foo.1 ])) a.c:11 28 {movqi_insn}
37 (nil))
38
Finally, at ira/reload phase, the (reg:QI 43) is assigned r24,
which does not satisfy the 'lsl' instruction constraint.
So a new insn-24 is created.
$ vi a.c.198r.reload
44 (insn 24 5 6 2 (set (reg:QI 24 r24 [orig:43 foo.1 ] [43])
45 (reg/v:QI 4 r4 [ foo ])) a.c:11 28 {movqi_insn}
46 (nil))
47
48 (insn 6 24 7 2 (set (reg:QI 24 r24 [orig:43 foo.1 ] [43])
49 (ashift:QI (reg:QI 24 r24 [orig:43 foo.1 ] [43])
50 (const_int 1 [0x1]))) a.c:11 199 {*ashlqi3}
51 (nil))
52
53 (insn 7 6 8 2 (set (reg/v:QI 4 r4 [ foo ])
54 (reg:QI 24 r24 [orig:43 foo.1 ] [43])) a.c:11 28 {movqi_insn}
55 (nil))
56
I am not sure if there is a solution to this issue on avr target.
Maybe someone else who work on avr porting can improve it
in combine phase or machine description design.
