http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53976
--- Comment #4 from Oleg Endo <olegendo at gcc dot gnu.org> --- One option to get rid of the redundant clrt and sett in BBs that are reached with a conditional branch would be to add an SH specific RTL pass that analyses the BBs and eliminates the insns in question. Another option could be to try and inject artificial sett / clrt insns at the start of BBs that are reached by conditional branches, and then split them away to nops or output empty asm with insn length 0. The idea would be to let other already existing RTL passes figure out the redundant T bit sets. There is already a similar functionality in cse.c (cse_condition_code_reg), but it probably wouldn't kick in, since clrt / sett insns are emitted until the split1 pass before register allocation and cse2 runs before that. But still, maybe another RTL pass would figure it out. It doesn't necessarily need to be before register allocation, since the T bit is a hard-reg anyway.
