http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59679
--- Comment #17 from Uroš Bizjak <ubizjak at gmail dot com> ---
Some more analysis:
The target code expands non-bwx QImode store
;; MEM[(I8 *)_67] = _69;
via alpha_expand_mov_nobwx, where around line 2229 (config/alpha.c) target
address gets checked with "aligned_memory_operand" predicate. The pointer is
"reg/v/f:DI 115 [ arg0 ])", and its REGNO_POINTER_ALIGN is 64. This later datum
makes aligned_memory_operand predicate to return true.
The pointer alignment for reg 115 is set in mark_reg_pointer from
(insn 68 67 69 (set (reg/f:DI 134)
(mem/f:DI (reg/v/f:DI 115 [ arg0 ]) [2 MEM[(struct AV *)_p_36].sv_any+0
S8 A64])) scope-reduced.c:53 -1
(nil))
since reg 115 is used naked to access 64bit aligned value.
The above (insn 68) is defined in BB 11, where the only predecessor is BB 10 (a
switch), and the only successor is BB 15.
Hovever (insn 101):
(insn 101 100 102 (set (reg:SI 150)
(mem:SI (reg/v/f:DI 115 [ arg0 ]) [0 S4 A8])) scope-reduced.c:60 -1
(nil))
which assumes 64 bit pointer alignment, lives in BB 13. Again, the only
predecessor is BB 10, and the only successor is BB 15.
The initialization of reg 115 is in BB 4 from a memory location:
(insn 27 26 0 (set (reg/v:DI 115 [ arg0 ])
(mem:DI (plus:DI (reg/v/f:DI 76 [ p0 ])
(const_int -8 [0xfffffffffffffff8])) [27 MEM[(union ANY *)p0_16
+ -8B]+0 S8 A64])) scope-reduced.c:37 -1
(nil))
and since everything is inside a loop, it looks to me there is no way for GCC
to assume inheritance of pointer alignments in BB 13 from BB 10.
