https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61357
Bug ID: 61357
Summary: Patch for 60969 causes MIPS regressions in register
allocation
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: sje at gcc dot gnu.org
This patch (GIT hash c5d7f2f65740ad3659ec083daa6af1df3a6473a7)
2014-05-22 Vladimir Makarov <[email protected]>
PR rtl-optimization/60969
* ira-costs.c (record_reg_classes): Process NO_REGS for matching
constraints. Set up mem cost for NO_REGS case.
Causes some test suite failures for MIPS including
gcc.target/mips/umips-lwp-3.c
Here is a modified version of umips-lwp-3.c:
void foo (int *r4)
{
int r5 = r4[511];
int r6 = r4[512];
r4[2] = r5 * r5;
{
register int r5asm asm ("$5") = r5;
register int r6asm asm ("$6") = r6;
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
}
}
When compiled with: -S -mgp32 -fpeephole2 -mtune=m14k -mmicromips -O2
it used to generate a lwp (load word paired) instruction. But after
this check in it generates two lw instructions instead.
