https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63949
--- Comment #8 from vekumar at gcc dot gnu.org ---
This is complete patch for the first approach that I took (comment 6). This
patch fixes issues I faced while testing. But I have added extra patterns to
cater the sign extended operands with left shifts. This might impact other
targets as well :(
Now I am also exploring other possibilities instead of writing extra patterns.
diff --git a/gcc/combine.c b/gcc/combine.c
index ee7b3f9..80b345d 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -7896,7 +7896,7 @@ make_compound_operation (rtx x, enum rtx_code in_code)
&& INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
&& INTVAL (rhs) < mode_width
&& (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
- new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
next_
+ new_rtx = make_extraction (mode, new_rtx,
0, NULL_RTX, mode_width - INTVAL (rhs),
code == LSHIFTRT, 0, in_code == COMPARE);
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 97d7009..f0b9240 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1570,26 +1570,62 @@
[(set_attr "type" "alus_ext")]
)
-(define_insn "*adds_<optab><mode>_multp2"
+(define_insn "*adds_<optab><mode>_extend_ashift"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
- (plus:GPI (ANY_EXTRACT:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0))
- (match_operand:GPI 4 "register_operand" "r"))
+ (plus:GPI (match_operand:GPI 1 "register_operand" "r")
+ (ashift:GPI (ANY_EXTEND:GPI
+ (match_operand:ALLX 2 "register_operand" "r"))
+ (match_operand 3 "aarch64_imm3" "Ui3")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
- (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2))
- (match_dup 3)
- (const_int 0))
- (match_dup 4)))]
+ (plus:GPI (match_dup 1)
+ (ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
+ (match_dup 3))))]
+ ""
+ "adds\\t%<w>0, %<w>1, %<w>2, <su>xt %3"
+ [(set_attr "type" "alus_ext")]
+)
+
+(define_insn "*subs_<optab><mode>_extend_ashift"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+ (ashift:GPI (ANY_EXTEND:GPI
+ (match_operand:ALLX 2 "register_operand"
"r")
+ (match_operand 3 "aarch64_imm3" "Ui3")))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r")
+ (minus:GPI (match_dup 1)
+ (ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
+ (match_dup 3))))]
+ ""
+ "subs\\t%<w>0, %<w>1, %<w>2, <su>xt %3"
+ [(set_attr "type" "alus_ext")]
+)
+
+
+(define_insn "*adds_<optab><mode>_multp2"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (plus:GPI (ANY_EXTRACT:GPI
+ (mult:GPI (match_operand:GPI 1 "register_operand" "r")
+ (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+ (match_operand 3 "const_int_operand" "n")
+ (const_int 0))
+ (match_operand:GPI 4 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r")
+ (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2))
+ (match_dup 3)
+ (const_int 0))
+ (match_dup 4)))]
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
[(set_attr "type" "alus_ext")]
)
+
(define_insn "*subs_<optab><mode>_multp2"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
