https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154
--- Comment #2 from Terry Guo <terry.guo at arm dot com> ---
Hi Tom,
I enabled this optimization to thumb1 target cortex-m0 and found this IPA-RA
optimization doesn't consider the register clobber information attached to call
rtx and thus generated bad code. Here are the bad rtxs I extracted from the
dump of cprop_hardreg pass:
(insn 292 291 141 13 (set (reg:SI 4 r4 [orig:163 ivtmp.108 ] [163])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163])) 742 {*thumb1_movsi_insn}
(expr_list:REG_DEAD (reg:SI 12 ip [orig:163 ivtmp.108 ] [163])
(nil)))
(call_insn 141 292 142 13 (parallel [
(call (mem:SI (symbol_ref:SI ("f2") [flags 0x3] <function_decl
0x7f8182689100 f2>) [0 f2 S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
])
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/vshift-3.c:119
770 {*call_insn}
(expr_list:REG_CALL_DECL (symbol_ref:SI ("f2") [flags 0x3] <function_decl
0x7f8182689100 f2>)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))
(expr_list (clobber (reg:SI 12 ip))
(nil)))
(insn 11 10 12 13 (set (reg:SI 0 r0 [orig:170 ivtmp.130 ] [170])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163]))
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/vshift-3.c:121
742 {*thumb1_movsi_insn}
(expr_list:REG_EQUAL (symbol_ref:SI ("j") [flags 0x80] <var_decl
0x7f81827d0750 j>)
(nil)))
I checked the code in 'if (CALL_P (insn))' part in file regcprop.c and found
the algorithm doesn't consider the '(expr_list (clobber (reg:SI 12 ip))' in
insn 141 which makes current algorithm think it is safe to propagate ip from
insn 292 to insn 11.
The case is from gcc regression test and compiled with option "-mthumb
-mcpu=cortex-m0 -O3".
