https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64617
Jakub Jelinek <jakub at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |vmakarov at gcc dot gnu.org --- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> --- The patterns in question are (define_insn "<mask_codefor><avx512>_vec_dup_gpr<mode><mask_name>" [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v") (vec_duplicate:VI12_AVX512VL (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "vm,r")))] and thus ought to support both HImode MEM as well as GPR. (insn 60 242 62 4 (set (reg:V32HI 114 [ vect_cst_.38 ]) (vec_duplicate:V32HI (reg/v:HI 169 [ a1 ]))) 4194 {*avx512bw_vec_dup_gprv32hi} (expr_list:REG_DEAD (reg/v:HI 169 [ a1 ]) (nil))) (insn 62 60 64 4 (set (reg:V32HI 129 [ vect_cst_.41 ]) (vec_duplicate:V32HI (reg/v:HI 171 [ a2 ]))) 4194 {*avx512bw_vec_dup_gprv32hi} (expr_list:REG_DEAD (reg/v:HI 171 [ a2 ]) (nil))) ... Vlad, can you please have a look?