https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697
--- Comment #1 from Matthew Wahab <matthew.wahab at arm dot com> --- I'm working on this but it isn't obvious how to fix it. The strong barriers aren't needed for the __atomics and will have an effect on performance so simply strengthening the MEMMODEL_SEQ_CST implementation in the backend isn't a good solution. It looks like the __sync builtins are always expanded out to the __atomics. This is done in the middle-end and there doesn't seem to be any way for a backend to intervene. I'm currently preparing a patch that introduces a new MEMMODEL tag to coretypes.h/memmodel to specify the __sync style full barriers. This can then be used in the __sync to __atomic expansions and, because the MEMMODEL argument to the __atomics is eventually passed to the backends, this is enough to enable backends to know when the stronger barrier is needed. The drawback with this is that a number of backends need to be updated to recognize the new MEMMODEL tag. For each, the minimum change is to make the new MEMMODEL tag a synonym for MEMMODEL_SEQ_CST. The backends that would need updating are arm, aarch64, i386, ia64, pa, rs6000, s390, sparc. (A subsequent patch would make the aarch64 backend generate the stronger barrier for the new MEMMODEL tag.) If there's a better way of doing it, let me know.
