https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65787
Bug ID: 65787 Summary: [5.1 regression] Miscompile due to bad vector swap optimization for little endian Product: gcc Version: 5.1.0 Status: UNCONFIRMED Keywords: wrong-code Severity: normal Priority: P3 Component: target Assignee: wschmidt at gcc dot gnu.org Reporter: wschmidt at gcc dot gnu.org CC: bergner at gcc dot gnu.org, dje.gcc at gmail dot com, jakub at gcc dot gnu.org, rguenth at gcc dot gnu.org Host: powerpc64le-linux-gnu Target: powerpc64le-linux-gnu Build: powerpc64le-linux-gnu Created attachment 35337 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35337&action=edit Preprocessed source GCC 5.1 miscompiles the attached file. The POWER-specific vector swap optimization doesn't recognize a vector extract pattern because it's hidden inside a parallel with a clobber. As a result it doesn't adjust the lane to be extracted. I'm working on a patch to detect this case and fix it up. This is probably miscompiled by the latest 4.8 and 4.9 base code as well, since the swap optimization was backported recently. I have not yet verified this, though. It could be that this pattern is not created for those releases.