https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2015-04-28
Ever confirmed|0 |1
--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to James Almer from comment #1)
> The same apparently happens with bextr, blsi, blsr, and most (if not all) of
> AMD's tbm instructions. They set the ZF flag but gcc still generates a test
> instruction.
Please see the patch, attached in Comment #2.
While I can see the use (and benefit) to model the patterns that also set CC
register internally for BEXTR and BZHI instructions, I don't think other listed
instructions have clear usage scenarios to warrant additional patterns.
Can you perhaps show the benefit to have more insns modelled this way?
