https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66933
Georg-Johann Lay <gjl at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |gjl at gcc dot gnu.org --- Comment #1 from Georg-Johann Lay <gjl at gcc dot gnu.org> --- Created attachment 36019 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36019&action=edit Possible solution as combine patterns. Well, this optimization is very special. You could, of course: Index: avr.md =================================================================== --- avr.md (revision 226011) +++ avr.md (working copy) @@ -1695,6 +1695,39 @@ (define_insn "*oumulqihi3" [(set_attr "length" "4") (set_attr "cc" "clobber")]) +;; Proposed in PR target/66933 +;; "*mulqihi3.lsr7" +;; "*umulqihi3.lsr7" +(define_insn "*<extend_u>mulqihi3.lsr7" + [(set (match_operand:HI 0 "register_operand" "=r") + (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a")) + (any_extend:HI (match_operand:QI 2 "register_operand" "a"))) + (const_int 7)))] + "AVR_HAVE_MUL" + "fmul<extend_s> %2,%1 + mov %A0,r1 + clr %B0 + rol %B0 + clr __zero_reg__" + [(set_attr "length" "5") + (set_attr "cc" "clobber")]) + +;; Proposed in PR target/66933 +;; "*mulqihi3.asr7" +;; "*umulqihi3.asr7" +(define_insn "*<extend_u>mulqihi3.asr7" + [(set (match_operand:HI 0 "register_operand" "=r") + (ashiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a")) + (any_extend:HI (match_operand:QI 2 "register_operand" "a"))) + (const_int 7)))] + "AVR_HAVE_MUL" + "fmul<extend_s> %2,%1 + mov %A0,r1 + sbc %B0,%B0 + clr __zero_reg__" + [(set_attr "length" "4") + (set_attr "cc" "clobber")]) + ;****************************************************************************** ; multiply-add/sub QI: $0 = $3 +/- $1*$2 ;****************************************************************************** As you can see, this needs 1 more instruction (signed shift) resp. 2 more instructions (unsigned shift) because it is not known at the time that only the low part of the expression will be used. Hence the high part must also be computed. One more instruction might be needed due to the register class restriction "a" for FMUL instead of "r" for MUL.