https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50749
--- Comment #21 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Urja Rannikko from comment #20) > I'll add a note here that this seems to also affect the AVR target when it > is under register pressure and cant use Z or Y registers which can do Z+n > /Y+n addressing, it ends up doing really stupid things with X register > ... I don't know AVR, but if it has only two addr regs which can do post-inc loads, in your example a loop distribution is required. In other words, you need to use two loops, first with p1,p2 and second loop with p3. Because the calculation in the loop is simple, it would make sense. If the calculations in the loop are more complex, maybe not. It's similar to the problems in PR 53949.
