https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68991
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |jakub at gcc dot gnu.org
--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
You haven't provided preprocessed source, nor exact command line options.
GCC uses the ix86_legitimate_combined_insn target hook to disallow misaligned
memory into certain SSE instructions.
(subreg:V4SI (reg:TI 245 [ MEM[(const struct bitset &)FeatureEntry_21 + 8] ])
0)
is not misaligned memory, it is a subreg of a pseudo register, so it is fine.
If the replacement of the pseudo register with memory happens in some other
pass, then it probably either should use the legitimate_combined_insn target
hook or some other one. I think we have already a PR where that happens during
live range shrinking.
