https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69806
Bug ID: 69806 Summary: [6 Regression][SH] Combine doesn't see constant Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: olegendo at gcc dot gnu.org Target Milestone: --- Target: sh*-*-* Some time between https://gcc.gnu.org/ml/gcc-testresults/2016-02/msg00444.html and https://gcc.gnu.org/ml/gcc-testresults/2016-02/msg00698.html there seem to have been a combine related change which triggered: FAIL: gcc.target/sh/pr64345-1.c scan-assembler-not exts|extu|sha|shld|subc|xor FAIL: gcc.target/sh/pr64345-1.c scan-assembler-times shlr\\t 8 The following sub-test exhibits the problem: int test_int64_t_shift_2_4 (signed long long x) { return (x & (1 << 2)) == 0; } Before it would compile (with -O2 -m4 -ml) to: mov r4,r0 tst #4,r0 rts movt r0 Now it's: mov #30,r0 shld r0,r5 shlr2 r4 or r5,r4 mov r4,r0 tst #1,r0 rts movt r0 This happens only for SH targets which have dynamic shifts (SH3*, SH4*, SH2A). The dynamic shift insns need the shift count loaded in a reg and are expanded as such. Combine would then eventually arrive at the single bit extraction pattern: Successfully matched this instruction: (parallel [ (set (reg:SI 173) (and:SI (and:SI (lshiftrt:SI (xor:SI (reg:SI 4 r4 [ x ]) (const_int 4 [0x4])) (const_int 2 [0x2])) (not:SI (ashift:SI (reg:SI 5 r5 [ x+4 ]) (const_int 30 [0x1e])))) (const_int 1 [0x1]))) (clobber (reg:SI 147 t)) ]) However, now the (const_int 30) doesn't get propagated anymore and it tries: Failed to match this instruction: (set (reg:SI 173) (and:SI (and:SI (lshiftrt:SI (xor:SI (reg:SI 4 r4 [ x ]) (const_int 4 [0x4])) (const_int 2 [0x2])) (not:SI (ashift:SI (reg:SI 5 r5 [ x+4 ]) (reg:SI 170)))) (const_int 1 [0x1]))) .. for which there is no pattern. Thus the bit test doesn't get optimized.