https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70490
--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> --- (In reply to Jakub Jelinek from comment #3) > The question is if e.g. XMM aligned loads are atomic or not. If they are, > we'd have to use some pattern that would ensure RA etc. doesn't optimize > that into a GPR loads. They are not, as stated in Vol 3B, 8.1.1: An x87 instruction or an SSE instructions that accesses data larger than a quadword [64 bits] may be implemented using multiple memory accesses.
