https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71186
--- Comment #2 from Michael Meissner <meissner at gcc dot gnu.org> --- Author: meissner Date: Wed Jun 1 20:09:35 2016 New Revision: 237006 URL: https://gcc.gnu.org/viewcvs?rev=237006&root=gcc&view=rev Log: [gcc] 2016-05-31 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/71186 * config/rs6000/vsx.md (xxspltib_<mode>_nosplit): Add alternatives for loading up all 0's or all 1's. [gcc/testsuite] 2016-05-31 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/71186 * gcc.target/powerpc/pr71186.c: New test. Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 236935) +++ gcc/config/rs6000/vsx.md (.../gcc/config/rs6000) (working copy) @@ -776,8 +776,8 @@ (define_insn "xxspltib_v16qi" [(set_attr "type" "vecperm")]) (define_insn "xxspltib_<mode>_nosplit" - [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa") - (match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "wE"))] + [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa,wa") + (match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "jwM,wE"))] "TARGET_P9_VECTOR" { rtx op1 = operands[1]; [gcc] 2016-05-31 Michael Meissner <meiss...@linux.vnet.ibm.com> * config/rs6000/vsx.md (vsx_splat_<mode>, V2DI/V2DF): Simplify alternatives, eliminating preferred register class. Add support for the MTVSRDD instruction in ISA 3.0. (vsx_splat_v4si_internal): Use splat_input_operand instead of reg_or_indexed_operand. (vsx_splat_v4sf_internal): Likewise. [gcc/testsuite] 2016-05-31 Michael Meissner <meiss...@linux.vnet.ibm.com> * gcc.target/powerpc/p9-splat-4.c: New test. Added: trunk/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c trunk/gcc/testsuite/gcc.target/powerpc/pr71186.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/vsx.md trunk/gcc/testsuite/ChangeLog