https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78559
--- Comment #5 from amker at gcc dot gnu.org ---
(insn 37 35 39 7 (set (reg:SI 96)
(sign_extend:SI (subreg:QI (reg:SI 95) 0))) 86 {*extendqisi2_aarch64}
(expr_list:REG_DEAD (reg:SI 95)
(nil)))
(insn 39 37 40 7 (set (reg:CC 66 cc)
(compare:CC (reg:SI 96)
(const_int 0 [0]))) 392 {cmpsi}
(expr_list:REG_DEAD (reg:SI 96)
(nil)))
(insn 40 39 41 7 (set (reg:HI 93)
(if_then_else:HI (ne (reg:CC 66 cc)
(const_int 0 [0]))
(subreg/s/u:HI (reg:SI 81 [ iftmp.0_17 ]) 0)
(reg:HI 97))) 443 {*cmovhi_insn}
(expr_list:REG_DEAD (reg:CC 66 cc)
(expr_list:REG_EQUAL (if_then_else:HI (ne (reg:CC 66 cc)
(const_int 0 [0]))
(subreg/s/u:HI (reg:SI 81 [ iftmp.0_17 ]) 0)
(const_int 1 [0x1]))
(nil))))
-------------->
Trying 37 -> 39:
Failed to match this instruction:
(set (reg:CC 66 cc)
(reg:CC 66 cc))
Successfully matched this instruction:
(set (reg:HI 93)
(if_then_else:HI (le (reg:CC 66 cc)
(const_int 0 [0]))
(subreg/s/u:HI (reg:SI 81 [ iftmp.0_17 ]) 0)
(reg:HI 97)))
allowing combination of insns 37 and 39
original costs 4 + 4 = 12
replacement cost 8
deferring deletion of insn with uid = 37.
modifying other_insn 40: r93:HI={(cc:CC<=0)?r81:SI#0:r97:HI}
REG_DEAD cc:CC
REG_EQUAL {(cc:CC!=0)?r81:SI#0:0x1}
deferring rescan insn with uid = 40.
modifying insn i3 39: cc:CC=cc:CC
deferring rescan insn with uid = 39.
Note after combine:
40: r93:HI={(cc:CC<=0)?r81:SI#0:r97:HI}
REG_DEAD cc:CC
REG_EQUAL {(cc:CC!=0)?r81:SI#0:0x1}
cc register has been changed, and (cc<=0) != (cc!=0).
