https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78041
--- Comment #18 from wilco at gcc dot gnu.org --- Author: wilco Date: Fri Jan 6 14:26:06 2017 New Revision: 244161 URL: https://gcc.gnu.org/viewcvs?rev=244161&root=gcc&view=rev Log: With -fpu=neon DI mode shifts are expanded after reload. DI mode registers can either fully or partially overlap on both ARM and Thumb-2. However the shift expansion code can only deal with the full overlap case, and generates incorrect code for partial overlaps. The fix is to add new variants that support either full overlap or no overlap. Backport from mainline 2016-10-25 Wilco Dijkstra <wdijk...@arm.com> gcc/ PR target/78041 * config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants. Remove partial overlap check for shift by 1. (ashldi3_neon): Likewise. testsuite/ * gcc.target/arm/pr78041.c: New test. Added: branches/gcc-6-branch/gcc/testsuite/gcc.target/arm/pr78041.c Modified: branches/gcc-6-branch/gcc/ChangeLog branches/gcc-6-branch/gcc/config/arm/neon.md branches/gcc-6-branch/gcc/testsuite/ChangeLog
